A UDP connection target FPGA with LabVIEW

Similar Questions

• Software FPGA with LabVIEW 2013

  I have a system with a rotating computer "development" under Windows 7 and an NI PXI-1036 chassis with a PXI-8101 controller as well as a card FPGA PXI-7853R. Recently, I upgraded to LabVIEW 2011-2013 of LabVIEW. I kept LabVIEW 2011 installed just to make sure everything is still working on the new LabVIEW.

  Now, when I open my project in LabVIEW 2013 Project Explorer, my FPGA comes with a warning triangle yellow next to him (see attached photo). The warning says:

  "Software support for this target FPGA is not installed on the computer. You can view and copy elements into the project, but you can not compile any screw under the FPGA target, until you install support for the target. Refer to the documentation of specific material for more information on the proper drivers and for more information about the installation and configuration of the target FPGA ".

  Regarding the installed software, I have LabVIEW SP1 of 2013, 2013 of LabVIEW FPGA Module SP1, SP1 of Module 2013 LabVIEW Real-time, and Xilinx Compilation tools 14.4. On the chassis of the TARGET (with the PXI-8101 controller), I have attached a list of installed software.

  Interestingly, when I open the project in LabView 2011, no errors or warnings are present with the FPGA card. It is only under LabVIEW 2013 I see the warning. Did anyone see a glaring omission of software that could be the cause of LabVIEW raise this error? Thank you for your help.

  

  

  Best guess is that're missing you the driver for your FPGA device. Try to install the latest version of NOR-RIO (or at least the version supplied on your 2013 SP1 install disks). Have you installed device drivers at the time that you have installed SP1 2013 LabVIEW?

• [FPGA] Associate existing target FPGA with real hardware?

  I started to write the code to FPGA and to support this, I have created a 'new' device FPGA - i.e. a device in the project but not associated with any actual hardware.

  Now, a colleague has access to some real hardware and tries to run the code on this subject, but has resorted to the creation of another target FPGA from the existing FPGA device (real hardware) and copy of the hierarchy of the code of the other device 'virtual' on him. It is also having to copy/recreate elements such as FIFOs in the project hierarchy.

  Is there an easier way to simply link the target that we created in the first place with the actual hardware?

  Sorry, I thought that the question should pass a target FPGA to a project to another (existing) without having to recreate the FIFOs, clocks, and other resources.

  If your FPGA card lies in a real-time controller you can simply change the IP address of the system in real time (as from real IP of 0.0.0.0 or any other intellectual property on the real-time controller) to run on a particular system.

• Installation of the Module LabVIEW 2012 SP1 FPGA with LabVIEW 2012 SP1 64 bit on Windows 7 X 64 machine.

  I installed 32-bit and 64-bit LabVIEW 2012 SP1 on Windows 7 X 64 computer. After that, I installed SP1 FPGA Module. While module FPGA completely installed in the 32-bit version and could develop projects fpga, FPGA interface has not installed the 64-bit version. Anyone had this before question?

  The document 5WMF8NQ2 knowledge base says it's doable.

  I have tried to repair the installed module, remove and then reinstall the module. Nothing helped me to get the FPGA interface on a 64-bit host VI. Any suggestions? Addition of the individual screws through the range of editing functions like a tedious process and the palette is not completely functional.

  I solved the problem. Had to repair each driver separately for LabVIEW 2012 SP1 64 bit installed on the default drive. You may need to copy paste files to the folder that it installed in function.

• HELP - FPGA SPARTAN 3E-100 CP132 WORKS WITH LABVIEW FPGA?

  HI EVERYONE, GET ON IM TRYING TO USE MY FPGA WITH LABVIEW, BUT I DO KNOW THAT IF ITS COMPATIBLE, I INSTALLED THE DRIVERS, MODULE FPGA AND LABVIEW 2012, IM USING WINDOWS 7 32 BIT, AND AFTER I COMPILED ITS SAYS:

  LabVIEW FPGA called another software component, and the component returned the following error:

  Error code:-310601

  NOR-COBS: Impossible to detect the communication cable.
  Check the communication cable is plugged into your computer and your target. Also, verify that the proper drivers are installed.

  Thank you.

  =)

  Hi dvaldez2.

  LabVIEW FPGA offers no support for any material to third parties, other than the 3rd Spartan XUP Starter Kit. These are probably the drivers you downloaded.

  http://digital.NI.com/express.nsf/bycode/Spartan3E?OpenDocument&lang=en&node=seminar_US

  However, this driver supports only the Starter Kit Board itself (http://www.digilentinc.com/Products/Detail.cfm?NavPath=2, 400, 790 & Prod = S3EBOARD). You may not use the driver with any other Xilinx FPGAS.

  I hope this helps.

• 7953 FPGA with 6581 adapter world clock inputs

  I am very new to FPGA with LabVIEW design. I have a FPGA 7953 card that connects to the 6581 adapter. This brochure, looking the 6581.

  ( http://www.ni.com/pdf/products/us/cat_ni6581.pdf )

  on page 3, it says "Note: clock is connected to the world clock for the NI FlexRIO FPGA module entries. I think it means that DDCA, 67 of the 6581 pin, I can feed an external clock in which is accessible in my LabVIEW FPGA code to entries world clock of the 7953? I don't know what these entries world clock would be on the 7953. It would be one of the choices presented to me as shown in the attached picture?

  Sorry if this question is wacky...

  Hi JHaas,

  I think that I can't fully responding to your question.  Yes, you can introduce an external clock in the 6581, which is accessible in your FPGA code.  Take a look at this knowledge base article which has some more details on the pins to use, and how to use the clock in a timed cycle loop.

• FPGA for PC via UDP connection

  Hi all

  Background

  I am currently working on a project to interface an FPGA with a PC, to send a UDP load prepared on the FPGA for the PC. The FPGA is preparing a payload of 18 hexadecimal bytes from h00 8' to 8' h11 and then transmits it via a local network on port 1024, between the FPGA and a second network card in the PC, with static IP assigned to the second network card and the FPGA. Packages leave the FPGA and reached the PC (tested with wireshark) but the vi does not appear meet the payload and display it on the screen in the vi. The vi is based on that comes with labview and only has a few adjustments for most simply to write the final packages saved to a text file.

  Problem:

  Initially, when the vi was run the length of the chain kept evaluate to zero and so he perceived no bytes don't read from the port. I then inserted the flatten channel vi after the UDP read and before the comparison of string length (after reading something on the forum), now the length of the string is not evaluated to zero to 4 instead of this, I also changed the display to the spell option but the same 4 Hexagon keep coming through '0000 0000 0000 0D0A' , but they are not those who have been sent from the FPGA (are they an error message?) and not those taken over by wireshark. In summary, I seem to not be able to read the data of the UDP payload in Labview.

  I tested the VI locally using the Protocol UDP send labview vi and vi (slightly) custom receiver and it still works. The receiver that VI is attached.

  Any suggestions would be great,

  Thank you

  James.

  You can share the wireshark log (preferably in a format based on text that I did not install Wireshark)?

  Are you sure that is no firewall problem? If you are using a firewall, disable it completely for this network card or at least ensure that it accepts connections on UDP Port 1024.

  In addition, set the UDP sender VI on another computer and see if you are still receiving data. If it works, compare logs wireshark compared to what is sent by the FPGA and search for differences. If this does not work, then you have a network like a firewall problem.

• Model a block synchronous dual-port RAM with LabVIEW FPGA

  This question caught my attention recently.

  I am trying to model a particular design element called "RAMB4_S8_S8" with the LabVIEW FPGA module. This element is a block synchronous dual-port RAM allowing simultaneous access to two ports independently from each other. That being said, a port can perform read/write operation to this RAM while at the same time, the other port might be able to do the same thing. There are two opportunities of possible port conflict, however. The first is when both ports are trying to write to the same memory cell. The other scenario is when a port writes in a cell memory while at the same time the other port reads from it. Other than that, everything should be a legitimate operation.

  In order to reproduce this I select memory block that is integrated into my FPGA target. An interface is configured to be the playback mode, and the other is set to write fashion. For the option of arbitration, I let the two interfaces to be "arbitrate if several applicants only. Then I got a compiler error when I tried to run my FPGA code for this model in a SCTL. The error message is something like "several objects to request access to a resource through a resource configured with option interface" arbitrate if several applicants only ", which is supported only in the single-cycle Timed loop if there is only a single applicant by interface.

  This error goes away if I replace the SCTL with a simple while loop, but not what I would like to implement. So I wonder if there is a better solution to this problem, or is it just the limitation of the LabVIEW FPGA module.

  Thank you.

  Yes, you can use a form of conduct to perform the operations you want in the generations clock cycles, but all the code is inside a single SCTL. Basically, read the first address and storing in a register in a single cycle and then read the second address in the second clock cycle. This would allow you to two readings of valid memory every clock cycle 2. I have included a crude extract to illustrate the concept. The case selectors are identical with address A being connected to the memory in the true case, B in the case of fake address. Your biggest model memory dual port will be intact, but it will operate at 1/2 rate.

  Take a look at the white paper that provides more details on the construction of memory:

  Data on a target FPGAS (FPGA Module)

  The ball on the memory block indicates that memory block double port cannot be applied in a configuration of reading, which is a double ROM. access read/write port must be imitated with custom code.

• NEITHER 9512 with Labview FPGA Interface

  Is it possible to use the NI 9512 stepper with Labview FPGA interface drive unit or is it only possible to use it with the interface of scanning? When I try to add the module to a FPGA target, I get an error telling me that Labview FPGA does not support this module with the latest version of NOR-RIO, but I have the latest version of OR-installed RIO.

  Hi Checkit,

  You're right - the 9512 cannot currently be used in FPGA. There is an error in the documentation. The 9514 and 9516 can, however.

• Unable to connect target RT in the LabView project

  Hello

  I use time LabView real-time 8.5 on a desktop PC. I see the target at MAX where I can change the network settings on the target and use FTP without problem. But it is impossible to connect to the target in a LabView project.
  The error of the target journal wrote:
  ####
  #Date: Monday, June 9, 2008 03:04:29
  #OSName: PharLap
  #OSVers: 13.0
  #AppName: PH_EXEC
  #Version: 8.5
  #AppKind: AppLib
  #AppModDate: 09/06/2008 06:55 GMT

  LVRT. DLL loads the address: 0x003EE000

  Can someone help me?

  Thanks in advance

  Hello everyone.

  The problem is solved! The reason of my problem is that LabView RT 8.5.0 supports no more than 2 GB of RAM installed on the computer, as described in this document.
  My RAM GB setting the things that were not possible before:
  -to connect to the target in a LabView project and deploy the code.
  -to activate the multiple core processor in the BIOS of the machine

  I said that the withdrawal of the USB keyboard is useful. Indeed with my keyboard plugged in, when I install other software as server VISA for example, MAX do not recognize the target automatically, I have to add it manually by specifying the IP address and I can not connect to the target in a project of LV.
  Unplug the USB keyboard (and other devices) to solve this problem.

  Good day...

• Target FPGA. help with sbrio 9631

  I am trying to connect to the analog I/o of my sbrio 9631. I'm trying to follow this video http://www.youtube.com/watch?v=q3-WGrnVnxM

  37 seconds, his project menu has two folders under the fpga target call anolg input and output analog. When I look at my project menu I don't have these files. the single folder target fpga for me is e/s on board. I use the same sbRIO as in the video. Any ideas? the attached pictures are of my project and its menu.

  
  

• Raspberry PI connected with usb for laptop with Labview

  Hello

  Please allow me to introduce myself: my name is Bob and I just graduated from the Bachelor of applied science (Physics), in the Netherlands. In education, I followed a course of programming in Labview. However, the course was not very well if I want to start from scratch. (my programming skills are very poor).

  My goal is to learn the basics of programming in Labview. I want to measure the temperature with a probe for example and read this in Labview. I need a data acquisition for this system. I have a raspberry PI in my possession and I was wondering if I could use it to read the temperature from the USB port of my laptop using the PI raspberry. Is this possible? And I have to run some sort of program on the raspberry PI? Or I could better use another device (Arduino maybe?).

  I hope someone could help me to help me get started with Labview. I'm looking forward to learn how to work with Labview and launch a few projects.

  Thanks in advance,

  Bob

  Are you comfortable with writing code on the invoice, pro forma raspberry? This is where you write the code for the acquisition of data and code to send it on the usb as a RS232 serial port. The LabVIEW program would receive all this and it is a very simple program. There is a tool called Linx box that does all this for the arduino.

  https://www.labviewmakerhub.com/doku.php?id=libraries:Linx:start

• CRIO 9031 UDP connection

  Hello

  Anyone know if a cRIO 9031 can be set to read a UDP port? I put my cRIO as an FPGA and I do not see the function of UDP connection anywhere. I have walked through and found no examples either. The PIC of these loopholes is attached. Do I need additional software installed in Labview. I'm using LabView 2015 SP1

  Any help is appreciated.

  Hi CEAR,

  It can, but not on the target FPGA.

  The VI you have created is under the FPGA target in the project tree. These support fewer functions than the parties in real time or office that is why you do not find the pallets.

  If you create a new VI by clicking to the right where it says 'Nor-CRIO9031-Test' to the place where it says FPGA and create a new VI then you create a VI in real-time. These can do things more screws can including UDP.

• NI 9148 with LabView module detection

  Hello

  I got the task of creating a deployable (compiled) software to a DAQ system with NI 9148 Ethernet RIO basket background and various modules. The user must have the ability to change the module type and the location of the different tests, so the application must detect (or the user specify) what modules are at what positions.

  I watched the blockset CRY, however this chassis is not supported and the lowest level blocks are protected. Is it possible to read the serial number of the modules connected to the 9148 OR position, type, and if all goes well?

  Thanks for any help!

  Hello Soonxaf,

  What are you helps as a controller-is this RT or Windows? Are you planning on the use of analysis of RIO or LabVIEW FPGA engine?

  If you plan use the analytical engine, so this should help you get started:

  Tutorial: Discovery, Configuration and programming access of the CompactRIO Scan Mode to IO with LabVIEW

  http://www.NI.com/white-paper/9351/en

  Kind regards

• CRIO-9073 is compatible with LabVIEW 8.5.1?

  I just got a cRIO-9073 and a cRIO-9074.

  When I set up, both of them appear correctly in MAX.

  When I add them to a project LabVIEW, the cRIO-9073 does not show the target FPGA. The cRIO-9074 shows.

  I'm using LabVIEW 8.5.1, is compatible with the cRIO-9073?

  Thanks for any help.

  Michel

  Hi Michel!

  According to this link, the interface FPGA and Scan of the cRIO 9073 are only supported in LV 8.6 using the NOR-RIO 3.0 driver.

  The link where you can check the compatibility is:

  FTP://FTP.NI.com/pub/DevZone/tut/crio_software_versions.htm

  Good day!

  Oswald Branford