Add multiply Xilinx IP Core

I'm traing to get the Xilinx CoreIP version of a multiplication add function and operation (Virtex 5 target LV 2012 SP1).

When I set up as I think the result is average offshore.  I can get the multiply part to work but I can't get the adding part works correctly, I have of course a few alignment issues.

The signals I want to work with (a * b) + c are

a = +-16, FXP-7

b = + 12.0 FXP

= +-16.1 c

How am I supposed to put in place the entries so that the numbers can be calculated?  I can get a * b so that the exit after bitshifting-7 is correct, but then the value when adding the parameter c is average offshore (probably 7 bits off, but I don't know how to fix it).

Shane.

The Xilinx core does not have the representation of FXP. He knows just the bit patterns. Therefore, take care of the alignment of the forest.

<+-,16,-7>* <+,12,0> =><+-,28,-7>

Now, we must add a number that corresponds to the representation of the bit. If the number you want to add is <+-,16,1>you for quarter-12-bit to have the correct word length (16-28), then quarter - an another 8-bit to fix the bits of the integer (-7 to 1). This is a total change of 20. Therefore convert c in <+-,36,1>and pass this number.

Tags: NI Software

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