Areas of clock in the FPGA examples

I was looking through some examples of LabVIEW FPGA and I fell on the example of Crossing Clock domains.

In this example, there are 4 screws; FIFOs.vi; Global Variables.vi; Local variables.VI; and Registers.vi. In each of these screws, there is a timed loop which runs at 160 MHz.

How is that possible? Since the clock on the FPGA is only 40 MHz. did I miss something?

On the FPGA target, you can right click on the clock of 40 MHz and create a derived clock which can be a multiple where for a fraction of the base clock (40 MHz).

160 MHz is a trivial example of 4 times the base clock.

Tags: NI Software

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