Broken thread - FPGA Interface Node error

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• Error-63101 when executing the FPGA Interface C API Generator in LabVIEW 2012

  I'm using LabWindows CVI 2012 and 2012 LabVIEW FPGA module.  I try to use the FPGA Interface C API generator and I get the following error from a freshly generated .lvbitx bitfile.  I use the local server compiles on my PC.

  Error-63101

  NOR-RIO: A valid .lvbitx bitfile is required. If you are using a valid .lvbitx bitfile, the bitfile maybe isn't compatible with the software you use. Determine which version of LabVIEW was used to make the bitfile, upgrade your software to this version or later, and then try again.

  The problem occurs when executing CVI or LabVIEW.  I was able to do this earlier when I was compiling the FPGA in LabVIEW with the API generator 2011 downloaded from the Web site.

  A bit of weirdness in my setup, it's that I charged it off downloads from the website (latest files after 2012 NIWeek) rather than the normal distribution DVD.  I installed LabVIEW, so NI RIO, then the Xilinx tools compatible with 2012.  It works very well when you talk to the FPGA to a LabVIEW vi running on my Windows PC to the host.

  Any suggestions?

  Problem solved.  I had to download FPGA Interface C API generator 12.0.  It works now.

  I would have thought that if a product was called on the menu in LabVIEW 2012, it would be prompted to upgrade to a compatible version, when I installed LabVIEW.  The old version is not compatible with version 3.0 bitfiles, as identified on the following lines at the top of the .lvbitx file:

  
  
   3.0

• FPGA Interface C API, error-63105, OR-RIO: C/C++ identifier is already in use and cannot be created.

  Hello

  Installation program:

  1 x the NI PCIe-7841R

  When I am trying to automatically generate a C++ API for my top FPGA VI using the FPGA Interface C API 12.0 I get the following error.

  Error-63105

  NOR-RIO:

  The "NiFpga_FPGATop_IndicatorBool_DMAFIFOtimeoutoccured" C/C++ identifier is already in use and cannot be created.

  Anyone know what this means? Is there some kind of limitation on the appellation of front interface controls?

  /Mola

  Problem solved.

  I had placed two flags with the same name on the front panel - by mistake. It builds the FPGA without errors, but the C API generator was not in favour of that.

  / Mola

• NEITHER 9512 with Labview FPGA Interface

  Is it possible to use the NI 9512 stepper with Labview FPGA interface drive unit or is it only possible to use it with the interface of scanning? When I try to add the module to a FPGA target, I get an error telling me that Labview FPGA does not support this module with the latest version of NOR-RIO, but I have the latest version of OR-installed RIO.

  Hi Checkit,

  You're right - the 9512 cannot currently be used in FPGA. There is an error in the documentation. The 9514 and 9516 can, however.

• mode scan interface - 805 error

  Hello

  I am a beginner system Compact RIO. The on I have a few questions scan mode interface.

  The only plug-in hardware is

  The cRIO-9012 controller and chassis integrated cRIO-9101

  a map AI 9205

  a card DIO 9401

  I would like to use the scan interface mode to understand the functioning of the cards, the in FPGA interface mode, it takes time for the compilation.

  The chassis does not support the interface mode scan, so I set up 2 cards variables individually using the I/O. Then I create the VI United Nations simply to read the voltage level of the card HAVE. I get an error - 805: source of synchronization, synchronize with the scan engine.

  I also checked in MAX, scan of OR soft the engine is installed.

  Could someone tell me this problem?

  Thanks in advance.

  Lily

  
  

• Cannot find the HDL Interface node

  I have MyRio and LabView 2014 with all modules installed and updated to date.

  Xilinx 2014 is also installed and I can compile for FPGA.

  However, in the block diagram I find interface HDL node for the import of VHDL code. As see you in the second screenshot.

  How can I solve this problem?

  

  

  There are no node integration IP in 2014 of LabView. Use instead the HDL Interface Node.

  Yes I used the HDL Interface Node and it has worked very well.

• Safe multithreading NI FPGA Interface C API?

  Hello

  I use the FPGA C API interface to communicate with the software labview on my FPGA OR. Some calls take a while to run, for example, reading on a FIFO so long timeout. So far, I assumed that the interface was not safe multithreading. It has now become annoying given the timeout problem described above. Try simply was not good, it can take a long time to create a "collison.

  Is the FPGA interface safe multithreading C API? Or, more specifically, the functions of FIFO reading can be called in parallel with read/write variables on the FPGA?

  Thank you.

  Hello MKAP,.

  It has been a while since I used the NI FPGA Interface C API, but it is what I remember and seem to be able to remember (and also found in the documentation):

  Functions related to the unloading and loading of the library are not thread-safe:

  http://zone.NI.com/reference/en-XX/help/372928D-01/CAPI/functions_required/

  On itself, this should be a problem:

  Your application should require that the NiFpga_Initialize is called before any other function associated with function calls NIFpga.

  In a similar way that unloading (NiFpga_Initialize) lof NiFpga brary should occur only when you are finished using it.

  With regard to multithreading, you must also keep in mind its mono-thread interrupts IRQ (if you plan to use them):

  http://zone.NI.com/reference/en-XX/help/372928D-01/CAPI/functions_interrupt/

• Sharing of Variables does not not under an FPGA interface?

  Hi all

  I have a controller 9074 cRIO 9074 chassis.

  I defined a number of variables shared under my RIO controller and writing a UI VI in my host PC, where I feed some variables of network shared in RIO and get another return to RIO on the front panel of my host. Naturally, the VI which deals with read/write variable network data to IO channels real is under my RIO controller.

  The problem is that, although everything seems to work fine when my RIO is set to the interface of the Scan Engine, the same screws give the following error message when I pass my RIO FPGA interface dependent.

  -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

  Possible reasons:

  CompactRIO: (Hex 0xFFFF0000) unable to communicate with the module. Re-insert the module and check the connections. If the chassis is in Interface FPGA programming mode, make sure that you have opened a FPGA reference bitfile or VI FPGA with the load of the Interface of scanning for the module you are trying to access using the scanning Interface.

  This error or warning occurred when writing the following shared Variable:
  \\AMR-cRIO9074\B1-DO\JCV1_C1_B1
  \\160.40.15.231\B1-DO\JCV1_C1_B1

  -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

  Note that I get this error message for each channel of e/s that I call my RIO. Also note that it is there still no reference FPGA currently in any of the screws... I want to solve the problem is because later, I'll have to add some FPGA in my code, so I can not just impersonating my RIO scan interface...

  Any help would be appreciated,

  Harry

  When you disable scanning on the cRIO platform engine, you must have some runing FPGA code.

  There is noway that knows your controller on any module, and he can't read anything from any module.

  If you do not have an FPGA vi, which sends the values of a port of the module on your controller, you need to do active Scan Engine.

  The error message clearly indicate that you must have an open reference FPGA vi or analytical engine to be able to read the values of and to a module.

  You are able to have custom analysis engine and a footstool of FPGA code at the same time on an FPGA.

  Is there a reason you do not run with the scanning engine?

• General questions about FPGA Interface C API 2.0

  I developed an application in LabVIEW FPGA 2011 on a Board of the R-Series PXI and a host application LabVIEW 2011 Windows XP to communicate with him via DMA FIFO.  I'm trying to adapt the interface to CVI 8.1 (preferred) or CVI 2009 using the Interface of FPGA C API 2.0.  The example of FIFO that it stores in the directory C:\Documents and Settings\All Users\Documents\National Instruments\FPGA Interface C API\Examples\ gave me a few questions:

  1. The functions NiFpga_WriteFifoI16 and NiFpga_AcquireFifoWriteElementsI16 are two different ways to do the same thing? I wasn't clear where I do the extra copy if you use NiFpga_WriteFifoI16. I guess the combination of NiFpga_AcquireFifoWriteElementsI16 with NiFpga_ReleaseFifoElements is the way to go if I want to stay out of trouble.
  2. I intend to call NiFpga_Initialize and NiFpga_Open in an initialization function that gives the word initially, then keep the session handle in calls to other functions.  The session handle is always not null when it opens successfully?  Could I use it as a test to make sure that I have a session valid before calling any other functions-example:
     If (session) {NiFpga_WriteFifoI16 (...)}
  3. Interface of FPGA C API 2.0 is only announced work in CVI 2009 up on.  If I include NiFpga.c and .h in my project CVI 8.1, it seems to compile fine, but I did have the chance to integrate yet.  Is there something specific that would make CVI 8.1 not work?  Our deployment environment of difficult application CVI upgrades

  -Jim

  Jim,

  With regard to your questions:

  1. Yes, these two functions are the same, however there is a big difference between the two. NiFpga_AcquireFifoWriteElementsI16 acquires, prepares and publishes FIFO elements to avoid the need to write the first in a buffer allocated by the separate user, then copy the contents of the elements in the memeory host buffer. Considering that, in the NiFpga_WriteFifoI16 does not work. So the NiFpga_ReleaseFifoElements should always be used with the NiFpga_WriteFifoI16. The example is just showing how the code should be used, but is not necessarily displayed works should be used together. I understand perfectly why he was confusing.

  2. the best way to ensure you have a valid session is by using the NiFpga_IsNotError() function. I've attached a screenshot of the example code that illustrates how best to achieve this and inserted the image below.

  

  3 regarding using CVI 8.1, there is nothing in particular, which would make your code does not work in point 8.1, but we can guarantee that C API 2.0 will work correctly with 9.0.

  Kind regards

  Larry H.

• Broken the FPGA VI but the empty error list

  Hello!

  I'm trying to run a vi which includes a 'Open FPGA VI Référence' function. However, an error and it says that "not compiled FPGA VI. When I try to compile the FPGA VI a message saying "The VI is broken". I try to run the FPGA and when appears in the error list, there is no error or warning in the list, although the name on the fpga includes the Red 'X' ('show warnings' is checked). Any help?

  I'm using Labview 2013.

  Pablo

  Hi Pablo.

  Sorry for my delay in responding, you managed to get the respected FPGA.vi yet?

  To answer your questions, if the project is ok with an empty FPGA.vi, then in theory, your hardware is configured ok. However, due to the vi being blank, you haven't tried to use one of the modules on your system, so it can introduce errors. The most common mistake is differentiation of mode Scan Mode/FPGA by installing the project in the first place. Also be aware that not all FPGA targets supports everything, for example some dislike for the rows that have an index to calculate the number of iterations, rather than a constant wired at the entrance to "n".

  Out of curiosity, why you place every measure in the DMA separately and also specify address? Is there a reason you don't just place all the measures in a table and put everything in the DMA, then divide the table on the other side?

  Generally speaking I don't think that incorrect programming should never cause LabVIEW crashing and you should always report the problem to the OR in order to take a look and see if they can fix it.

  Hope that you managed to get your problem sorted and again sorry for the late reply.

  Darren.

• LabVIEW FPGA CLIP node compilation error

  Hello NO,.

  I work on an application for my Single-Board RIO (sbRIO-9601) and faced with a compile error when I try to compile my FPGA personality via the ELEMENT node.  I have two .vhd files that I declare in my .xml file and all at this point works great.  I add the IP-level component to my project and then drag it to the VI I created under my FPGA.

  Within the FPGA personality, I essentially have to add some constants on the indicators and entries CLIP to my CLIP out and attempt to save/compile.  With this simple configuration, I met a compilation error (ERROR: MapLib:820 - symbol LUT4... see report filling for details on which signals were cut).  If I go back to my VI and delete indicators on the output (making the output pin of the CLIP connected to nothing), compiles fine.

  I've included screenshots, VHDL and LV project files.  What could be causing an indicator of the output of my VI to force compilation errors?

  Otherwise that it is attached to the output ELEMENT, a successful compilation...

  

  After that the output indicator comes with CLIP, compilation to fail...

  

  NEITHER sbRIO-9601
  LabVIEW 8.6.0
  LabVIEW FPGA
  Windows XP (32-bit, English)
  No conflicting background process (not Google desktop, etc.).

  Usually a "trimming" error gives to think that there are a few missing IP.  Often, a CLIP source file is missing or the path specified in the XML file is incorrect.

  In your case I believe that there is an error in the XML declaration:

  
    1.0
    RandomNumberGenerator
   
      urng_n11213_w36dp_t4_p89.vhd
      fifo2.vhd
   

  This indicates LV FPGA to expect a higher level entity called "RandomNumberGenerator" defined in one of two VHDL files.  However, I couldn't see this entity in one of two files.  If urng_n11213_w36dp_t4_p89 is the top-level entity, edit the XML to instead set the HDLName tag as follows:

  urng_n11213_w36dp_t4_p89

  Also - in your XML, you set the 'oBits' music VIDEO for output as a U32, however the VHDL port is defined as a vector of bits 89:

  oBits: out std_logic_vector (89-1 downto 0)

  These definitions must match and the maximum size of the vector CLIP IO is 32, so you have to break your oBits in three exits U32 output.  I have added the ports and changed your logic of assignment as follows:

  oBits1(31 downto 0)<= srcs(31="" downto="">
  oBits2(31 downto 0)<= srcs(63="" downto="">
  oBits3(31 downto 0)<= "0000000"="" &="" srcs(88="" downto="">

  Both of these changes resulted in a successful compilation.

  Note: The only compiler errors when you add the flag because otherwise your CUTTING code is optimized design.  If the IP is instantiated in a design, but nothing is connected to its output, it consumes all logic?  Most of the time the FPGA compiler is smart enough to get it out.

• ERROR, called from the thread NON-INTERFACE QThread

  I am trying to load an image using QtConcurrent:map at the same time and I received this error.

  WARNING: ApplicationPrivate::context: ERROR called NON-INTERFACE QThread thread (0xf9ff68, name = "thread (pooled)" ")
  Fatal: ApplicationPrivate::context: method called from the UI thread

  I simplified the code as follows:

  imagescaler::queuescaling{
  ..    mimageScaling = new QFutureWatcher(this);
  mimageScaling->setFuture(QtConcurrent::mapped(mImageList, scaledImage));
  ..
  }
  
  Image scaledImage(QString file_name) {
     QImage qImage;
     bb::ImageData imageData(bb::PixelFormat::RGBA_Premultiplied, qImage.width(),
    qImage.height());  // causes error
    return imageData;
  }
  

  Anyone know what the problem is or how to work around?

  Thanks for point out the bb:ImageData.  Never noticed the incompatibility.  Image converts ImageData to initialization, so it does not create an error.  However, if I return an ImageData rather than the Image it does not crash.  I then simply convert ImageData of Image in the UI thread and it works very well.

  I'm curious to know why I can return a blank image and I can return an imageData, but I can't go back an Image that's been converted from ImageData.  Do not understand what can or cannot be done outside the UI thread.

• HDL Interface node from the IP Net efficiency

  Hello

  If I use Node Interface HDL to VHDL in VI FPGA code, it will be more effective than the IPs that are available on http://www.ni.com/ipnet/ ?

  Kindly guide me.

  Thank you and best regards,

  Rashid

  Hello r,.

  IP on IPNet will be written using the CLAMP which is much better for the implementation of VHDL in your LabVIEW FPGA code.  The following document describes some of the differences between the two.

  http://digital.NI.com/public.nsf/allkb/ce502221933fcceb8625750000011fb5?OpenDocument

  Also, something to keep in mind, from LabVIEW 2010 HDL node will be deprecated so to ensure future compatibility, you're better the CLIP path.

• Industrial communications for CANopen - interface create error

  Hello

  I am trying to run a few basic examples, I found with the finder example in communication industrial directory - NOR - for CANopen-> cRio-> FPGA bitfiles-> CANopen_cRio_heartbeat.vi.

  But the block 'create an Interface' gives me the error 2147136667.

  I work with with module NI 9881 cRio. The module is connected to the robot from Festo.

  You please any idea what can cause this error?

  The text of says error:

  Possible reasons:

  You try to start an interface that is missing the bus for the transceiver power. Some physical layers on the material OR CANopen are fed internally, but others require an external power supply so that the port to operate. This error occurs when starting an interface on the equipment that requires an external power supply when no power is detected. Power supply right to your transceiver. Refer to the material of the NOR-Industrial communication CANopen Book for CANopen help for more information.

  See you soon

  Ivo

  Hello T.t,

  The 9881 must be fed outdoors. You can do with a CAN of junction box or with a Câble CAN.

  Concerning

• FPGA IO node and loop Question of Timing

  I'm having a lot of trouble to compile a very simple FPGA VI for a system for the acquisition of data on my cRIO (9075, using a single module 9205 cRIO, labview 2012 dev suite, xlinx13).

  At the end of compilation, the error occurs if and only if I use a block of i/o node FPGA.  This picture shows my very simple VI which fails to a compilation:

  

  When I compile, I get this error at the end:

  

  And here are the details of the error:

  

  It is also interesting to note that the 'Timing' summary says I need a clock of 80 MHz, when the on-board clock of 40 MHz.

  For comparison, when I remove the FPGA of e/s node and replace it with a constant, the compilation succeeds:

  

  The need of a clock of 80 MHz disappears also, according to the report of timing.

  Is this a problem with how loops work in FPGA?  I've been reading about "single-cycle timed loops" that guarantee a performance per clock cycle.  I don't have that kind of acquisition rate, and I guess the structure of loop, I created is not related to a single cycle because of the block of metronome, that I inserted.  I guess correctly?  Are there structures of loop for FPGA which is not related to a single clock cycle?

  I also wonder if this error is not to do with my code, but is rather an internal error of the software compilation NOR, in particular the 'niFpgaTimingViolation.py' script mentioned in the summary of the detailed errors.  I got labview 2011 and xlinx 12 installed on this computer before, but they uninstalled before the upgrade.  This is my first project in 2012.

  I appreciate the comments of the community NOR.  Let me know if my question needs further clarification.

  -Andrew

  I solved the problem.

  In case that someone looking for it later (error 61499 niFpgaTimingViolationMain.py that constraintdict is not defined).

  I did a complete uninstall and reinstall my entire LV 2012 dev suite.  Then the same VI used to compile failure began to pass compilation.  Apparently, I had a corrupt file somewhere.