cRIO-9118 FPGA and or cRIO-9022 RT.

Hi all.

Having trouble to get my design FPGA compile for the target.

The error is the overuse of the DSP blocks. 64 available on target...

Do I have to reduce to a minimum the number of blocks of multiplier?

Or can I somehow multiplex on DSP minimixe DSP multivariate use?

Thank you.

FPGA high speed multiplier Math must be set to LUT and not AUTO, because it will use DSP and not LUT car if there is too little of DSP.

This will reduce use DSP, but increase the use of LUT.

Tags: NI Products

Similar Questions

  • FPGA. What tool xilinx for Crio-9022 & 9030

    Hello. I will be compiling the programs of fpga on the Crio-9022 and 9030. You need Xilinx different compilers to do the task?

    With the help of LV ver14

    CRIO-9022 requires xilinxs 14.7 tool?

    CRIO 9030 requires the xilinx tools vivado 2013.4?

    Thank you

    Yes, it's because of the different FPGA series located on the backplane of the 9022 and 9030 cRIOs.  You can see this KB and this KBto see below why.

  • How to use the target FPGA and co. on the same chassis cRIO?

    I have a cRIO system consisting of a master chassis 9074 with several modules IO and EtherCAT 9144 slave unit.

    I want to run a CIE (see: http://zone.ni.com/devzone/cda/epd/p/id/5333) on the chassis of the master, this uses the analytical engine. At the same time I have to do some very urgent measures if I want to use the Board in hybrid mode, using analysis and FPGA engine at the same time (as described here: http://digital.ni.com/public.nsf/allkb/0DB7FEF37C26AF85862575C400531690.)

    But as soon as I add the FPGA target at one of the chassis, the feature of the ice on this chassis stops working. After some research, I found that the CIE can initialize is no longer the modules belonging to the frame that has the target FPGA on it. Error in the method Init of the CIE is: 65700 (indeterminate). This occurs when you try to use "for a more specific class' on the modules configured with a target FPGA on it.

    Someone knows what can cause exactly this problem and perhaps provide a solution/work around?

    Many thanks in advance.

    Hybrid mode requires you to have a bitfile compiled running on the FPGA to be able to read the Scan Interface IO Variables.  Move the target FPGA at the RT target module will allow Interface of scanning for this module, but the frame will always mode Interface of LabVIEW FPGA.

    To get fair access to the scan mode for the frame, right click on the chassis in the project, and choose Properties.  Then, modify the Scan Interface programming.  If you want to continue using the programming of FPGA and the Scan Interface set (hybrid mode), you will need to compile a bitfile (empty if you do not want programs on the FPGA again or containing your FPGA code).  By compiling, the support of the module scan mode for the modules under your RT chassis is compiled in your custom bitfile.  Then, on your VI RT, you need to use reference FPGA VI open to your newly compiled VI.  Once this VI is deployed and ongoing implementation, you get the data from you are the CIE.

    For more information, see this knowledge base article and Reference Interface of Scan CompactRIO and procedures.

  • OR Communication CANOpen cRIO-9022 (9853 CAN module) and EPOS2 MAXON

    Hi all

    I am implementing a control loop of speed on my motor Maxon EPOS2 controller, using the AOP, sent through my real time controller (OR cRIO-9022) with a DRUM module (9853).

    I set up the mapping of the PDO in the dictionary of the object of the EPOS2, so that each new RxPDO1 contains the new speed desired highlighted, and I try to use the simple example in the standard Canadian example directory criocanopenbaisc (downloadable for free here http://zone.ni.com/devzone/cda/epd/p/id/5474).

    Can I change manually in the object dictionary the value of the desired speed using the studio tool EPOS by logging in through the port USB the EPOS2 to my computer, but when I connect the EPOS2 to the port of cRIO CAN0 values recently sent has no effect.

    To try first the .vi file hung on the AOP read command, which is just after the AOP command write. I guess that means that no real PDO is sent via the CAN bus. However, I have excluded the diagram of the PDO 'read', now the file runs and ends but no command is sent to the EPIC. I can check with an oscilloscope that many similar digital waveforms are sent, as if no ACK signal has been received.

    After several attempts, I sent AOP structured in the following way:

     

    COB - ID (4 bytes containing the COB - ID for RxPDO1 U32 representation: 531)

    Updated value (4 bytes containing the representation of the value of the desired speed, U32).

    0 in U32

    0 in U32.

    The last two U32 are then sent to be consistent with the example of the nicanopenbasic of library OR.

    For the moment, a signal is sent (no more repetitive signals representative communication fault), but the values are not updated in the EPOS2...

    See you soon

    Double post

  • 9401 serving counter in cRIO 9022

    Hi all

    I use cRIO-9022 and 9401 is one of the modules of him. I want to use 9401 as counter in the FPGA VI. Is this possible? As the specialized digital Configuration option is not available when the module is moved to the target FPGA.

    Shrinivas

    Yes, you can, and many of us do on a regular basis.

    Good read from this link to help you get started.

  • The CRIO-9022 software installation

    Anyone can help with installing Software NI 9022 by MAX

    I connect OR cRIO-9022 with an Ethernet.

    I was faced with a time-out error and saying that whether online or not, to the extent of the im concern its connected in safe mode as he always has no software in it.

    Please see the attached file.

    It is probably a detail of networking.

    It seems that you have a link-local address on your cRIO (169.x.x.x) which means that you should always have your computer configuration using DHCP. If you have a static IP address on your computer, try to return to "obtain an IP address automatically".

    If this does not work, I will try to set a static IP address on your PC to install the software and the cRIO. Once you get the cRIO software installed, you can switch everything back to DHCP.

    Find instructions here:

    http://www.NI.com/gettingstarted/setuphardware/CompactRIO/firstuse.htm

    Kurt

  • CRIO-9022 controller does support LV RT 8.5.1?

    Hello world.

    CRIO-9022 controller does support LV RT 8.5.1?

    Thank you.

    Daniel R.

    CLD

    Hello Daniel,.

    This document indicates that you need 8.6 LabVIEW and NOR-RIO 3.1.0 for use the 9022 controller.

  • FPGA and digital i/o Modules

    Hi all

    We have NI 9421 digital input and digital output NI 9472 Modules. We can run these modules into a VI under the 9073 cRIO chassis. While we have added the FPGA target under the same chassis, we cannot use the modules. We also install the scan engine.

    How can we use FPGAS and i/o Modules at the same time?

    Once you add a target FPGA in CompactRIO chassis, when you deploy the code, the cRIO is configured for the FPGA mode, which requires a bitfile compiled to connect with the C Series modules.  Remove the target FPGA or changing the mode of chassis in the project and by redeploying must reconfigure the cRIO for scan Mode, which allows you to use the IO module directly from the RT VI.

    For more information, see this post.

  • What is the use of FPGAS and how it differs from the IO Modules

    Hi all

    Maybe it's a silly question for most of you.  But I have very less knowledge about the basic concepts of electronic (FPGA, real-time) to cRIOs. I know that FPGA

    can be used to generate circuits within the chip that helps by some logical functions.

    I've just started working in the cRIO.  My question is that we have Modules e/s making it outputs all the application entry.  So, what is the purpose of e/s in the FPGA.

    Lets consider that we entered for an application of RTD.  In this case the module NI 9217 itself exits 24 bits of data from the RTD measurement which may be the process of the LabVIEW VI.  What will be this FPGA between the i/o Modules and the processor will help in?  Also I want to know what type of communication is used to send data between the FPGA and host modules.

    Thanks in advance

    Ajay HI:

    Sorry, you do not have an answer to your original question. However, you are right about the benefits of the FPGA. You said, if you build pre-processing in the FPGA, you can unload a lot of potentially CPU calculations out of the host processor. In addition, the program running on the FPGA is highly deterministic and can run the code very quickly. So if you build a kind of guard or evanescent dog part of your application, the FPGA is a good place to put it.

    To answer your other questions, communication between the modules and the FPGA is generally above the SPI and the data can be transferred between the FPGA and host via DMA FIFO operating on the PCI bus or single point save access using read/write in the FPGA host Interface controls. You can also use interruptions in signal of disputes between the FPGA host.

    I hope this helps, but let us know if you have any other questions.

  • Number of DMA FIFO of items to read mismatch in the FPGA and RT

    Hi all

    I use myRIO, LV14 to run my application.

    Request: I have to continuously acquire data via FPGA and host RT process once every 2000 samples are taken. I use DMA FIFO (size 8191) to acquire data, use timeout property in the FPGA to eliminate the buffer overflow. I had followed cRIOdevguide to implement this part. An excerpt of what I put in place is attached. All code runs in the SCTL at 50 MHz.

    Question: Two or three times I met with this strange behavior, the FPGA FIFO gives continous timeout and the RT is unable to read the FIFO. The number of elements to set the property in the FPGA VI gives 0 showing that FIFO is full and no more can be written, but the RT, remaining items gives 0, so it is reading 0 (none) elements.

    Solution: I put a case where I'll write to FIFO (under the code) and if the number of elements to write is different from zero. It seems to work fine, from now.

    What confuses me, is that my FPGA VI said that FIFO is full (number of items to write 0 = FIFO) and gives a timeout error, but RT VI said that number of items remaining in the FIFO is 0 and therefore no data is read. No idea why this is so? My RT and FPGA VIs continues to run, but with no gains or to read data.

    A few minutes after you run the code, I've seen this behavior. No idea why this happens? I try to reproduce the behavior, and will update if I meet with her again. Sorry, I can't post my code here, but I guess the code snippets to explain some extend.

    Thank you

    Arya

    Edit: Even with the mentioned workaround solution, the problem persists, now that the FPGA written any of FIFO. And the RT VI is not able to read all the elements he sees 0 items in the FIFO. The FIFO continues to be in a State of timeout. So I guess that the problem is on the side of RT.

    Why it looks like you read from the FIFO even in two different places in the same VI, at the same time? If the lower reading throws the FIFO, it will never trigger the reset, which could lead to the situation you describe, I think (it's hard to tell from a few screenshots).

    Also, your logic seems too complicated. I immediately noticed that there is no reason to select the entry, the output of = 0 - simply use the 'equal to zero' output directly. On the side of FPGA, why you need check the number of items that you want to write? There's nothing wrong with writing in a FIFO that is already full. just the data won't get written.

  • LabVIEW FPGA and real-time communication module

    Hi all

    I created a small program in labview FPGA which gets continually distance from the HC - SR04 ultrasonic sensor. The rest of the robot program is written in the time module real Labview. Is it possible that the distance calculated by FPGA module to read in time real module.

    I used the FPGA just because there micro-deuxieme counter, which helps me get the distance from the ultrasonic sensor.

    Thanks in advance.

    There are many ways this can be done, according to your needs.

    See the help article transfer of data between the FPGA and host (Module FPGA) for a breakdown of each method.

  • Card FPGA and data acquisition synchronization

    Hi, we are control and data acquisition of several hardware devices (including Photodetectors and translational stages). Until last week, we used all the controls and acquisition using a PCIe-7852R FPGA board. However, we decided to move the acquisition part to a PCIe 6363 DAQ card to improve the sharpness of the tension. During the test, I found that the internal clocks in the FPGA and the DAQ cards are slightly inconsistent (not just a phase delay, but a difference in the period).

    I know because I have generated a square wave (period = 20) using the FPGA and gains using the data acquisition card (at a rate of 200 kHz, that is, 1 taste every 5). I have observed acquired place shifts 5 every 5 seconds approximately. Such a change does not occur if the production and acquisition is done using the same Board. Therefore, the only explanation is that the data acquisition and FPGA cards clock frequencies are different. According to my calculations, the percentage difference between their time clock must be 5/5 s = 0.0001%.

    Therefore, I wonder if there is anyway to synchronize clocks between them. Or, is it possible that I can drive the FPGA clock-based DAQ hardware, or vice versa? Also, please let me know if there is something trivial as I fix.

    Thank you very much.

    Kind regards

    Varun

    Hi Varun,

    my post was only one solution...

    Your data acquisition card may take an entry to control sampling of trigger. In this mode, samples draw on a rising edge of the external clock signal. As long as you stay within the limits of the DAQ (100 MHz for your card) material sampling works perfectly. There are even examples coming with LabVIEW explaining how to program your data acquisition card...

    This mode use you your FPGA as clock source sampling for data acquisition. Both will run on the FPGA clock in sync. When the FPGA is a bit out of 40 MHz, so it won't matter because both devices are triggered on the same clock signal...

  • What are the differences between LabVIEW and LabVIEW FPGA and LabVIEW RT

    I need a comparison of LabVIEW, LabVIEW FPGA, and LabVIEW RT

    Sorry, I misunderstood.

    LabVIEW RT (LabVIEW Real-time) combines graphical LabVIEW of programming with the power of a real-time operating system, allowing you to create applications in real time.

  • Connect mobile NI 9144 to the cRIO 9022


    Hi homer210788,

    EtherCAT is a deterministic communications protocol, so it is not all real way to communicate wirelessly with the controller and 9144.  Out of curiosity, what is your application, and why do you want to make wireless?

  • cRIO-9022 puerto RS232

    Hola, deseo saber if examples are para the closing of datos desde el puerto RS232 as el sistema Compact-RIO offers. MI purpose are control UN recirculado por medio este puerto (I have configurado el sistema CompactRIO y works well with the closing of señales from las Pestana, ahora quiero con entrada del RS232 driver test); Pero no he tenido exito poco con some the tests that he performed, of photos muchas gracias por information than can proporcionarme, sugerencia o examples. Saludos!

    Finalmente pude leer los datos as queria (el estaba en config del equipo detail). Thanks for the help

Maybe you are looking for