Data entry on the host VI without FIFO Massive?

Hi guys,.

First post on the boards and about two weeks in LV in time real/FPGA so be gentle!

I'm data capture of a system using a CRio 9082 and Converter A/D NI9215. The FPGA vi runs a timed loop (10 US or 100kS/s) that pulls in the data and sends them to a target-to-Host DMA FIFO (4096 long, single precision). Since I want to synchronize data for a TTL output, the FPGA also sends a True/False value through a port DIO (NI9402). So, for example, if I want a TTL of 100 Hz pulse and time of the loop is 10 US, then a complete cycle of TTL will last 1000 loops with the half cycle lasts 500 loops. Both the position in the LIFE cycle (0-1000) and the acquired data to that position in the cycle are intertwined in the FIFO. I have attached a picture of the VI.

The host vi simply reads the values of the FIFO, decimating the interlaced output and stores the data in a table for later processing. I have also attached a picture of the host vi. The problem is that the data acquisition time could be as high as 10 seconds, which would mean that the FIFO host-side would be long 2 million items!

SO my question is how to change the host vi so that rather than wait as the FIFO side host to be filled, its size can be reduced and yet not lose data points in the table fill? One can rightly wonder why I did things like that, but I found that fill a massive FIFO ensures that I do not lose the continuous position TTL data, but then I thought it was totally ineffective and some sage advice is necessary!

Thank you!!

My advice would be to do the following:

(1) configure FIFO depth to be quite large not to overflow during a regular operation, but don't try to configure it to keep your entire dataset in a single shot.

(2) If you send only the integers to the FIFO, do not configure it for double rooms.

(3) instead of voting for a whole dataset, you can read the smaller packets of the target and build them together on the host. Pop, a delay in your in a loop to read each 10/100 ms, 0 items via a FIFO Read, out of the remaining elements of wireless node to the number of items in a FIFO read node entry. It will take all that is in the FIFO at this stage. Using a registry to offset, concatenate the table with table of the previous iteration and stop all loop when the length of the array reaches the number wanted items.

You might need to play to ensure that the order of the data in the FIFO is not flipped depending on when you start and stop acquisition, but at least it's a start.

Tags: NI Software

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