Encoder FPGA Crio SSI Protocol

Hello everyone

Everyone works with encoder SSI and Crio FPGA Protocol? I wrote a simple program that try to apply this Protocol on Crio FPGA, but I get the chaotic data. I use a TTL-rs422 converter to transform (422) signal at the TTL for Internet signal high speed digital NI9401. Could someone help me? any suggestion?

Thank you

Francesco

Hi all

I solved my problem. I am able to read the angular position of an Eltra encoder with SSI protocol using labview FPGA.

Thanks for all the help

Francesco

Tags: NI Software

Similar Questions

  • Read an absolute encoder in cRIO 9076

    Hello

    I try to use cRIO 9076 and NI 9401 to read an absolute encoder (http://www.gpi-encoders.com/PDF/A58.pdf).  I hope that it is possible.  Please can someone advise if there are any example or a tutorial that explains how I can deal with the digital input data to get an output of numeric position?    Thank you.

    Hello:

    Are you using the A58-12 encoder? (It's the only one that looks like it will work with the 9401). If so, it returns data using the series SSI Protocol.

    You will need set up an output clock and the input of the 9401 SSI data line. For the reading of the data, there is an example of FPGA SSI on the community related to this knowledge base Article.

    Hope that helps out!

  • Crash when creating a new project FPGA cRIO

    When I want to create a new project with the wizard FPGA cRIO, Labview freezes and blocks ("development system Labview 8.6 had ceased to function".) The wizard detects my cRIO-9073 integrated controller, but when he tries to discover the CompactRIO chassis, the program hangs and stops automatically.

    In MAX, there is no problem discovering the FPGA chip in the cRIO-chassis (RIO0)...

    I tried to use the new FPGA Project Wizard in Labview 8.5. While searching for the cRIO chassis, the program does not freeze, but he says the cRIO-chassis cannot be found...

    When I want to manually select the chassis, I can only choose for the cRIO-9072 and cRIO-9074. There is no cRIO-9073-icon...?

    What I am doing wrong, or is this a bug?

    Kind regards

    Kenneth


  • FPGA CRio do not give good digital outputs

    I'm working on a project with the compact RIO fpga. I tried following the youtube tutorials and written tutorial, but I get no similar results in scanning FPGA interface.

    I have attached my project. Here's the signal that I get from the Basic VI, which is a digital IO defined as output in a while loop. Alongside this, there is a loop for fundamentally changing the frequency of the digital signal from the top down. But whatever number I put in the loop for, it gives me the same frequency.

    My thought process goes like this: If the CRio has a processing time of 40 MHz to a loop that cycles 400 times should give me a swing of 100 kHz output, which is not any number, I put in.

    Any help is appreciated.

    Thank you.

    LabVIEW is almost certainly that compile to loop out like dead code (nothing happens so LabVIEW gets rid of it). I advise to use the loop timer function if you are looking to change the frequency or put everything in a timed loop. All in a timed loop will execute a tick.

  • Is it possible to have a multiple FPGA cRIO system?

    I'm curios if it is possible to have a single cRIO chassis that can be extended with additional FPGA for calculations. Which means, I have more I/O but I algorithms take too much space and need a secondary FPGA to perform parallel processing. Data would be generated in the first FPGA and communicated to the second FPGA where additional processing takes place and then a command/response is returned to the first FPGA which will then be sent through the IO.

    I saw something "similar" to that in PXI: http://zone.ni.com/reference/en-XX/help/372831C-01/p2pstreamhelp/p2plv_topo_pipelinefpga/

    Although this solution depends directly on the SMU bus there the general feeling for what I want. However, I need this in cRIO. Is there a solution that I missed in my navigation of NI.COM?

    It would be OK if the solution uses one of the slots on frame cRIO.

    A cRIO chassis only has 1 FPGA on it.  You may be able to get an expansion chassis and pass data to it in order to do the treatment.  For what you're talking about, you probably want to add a few DIO so that you can directly communicate with the expansion instead of going through the RT chassis and the analytical engine.

    You can also get a cRIO with largest FPGA and/or your representative local to la OR the chance to see if you can get some time with a systems engineer OR that can help you optimize your code to fit on a single FPGA.

  • Repeated values in the measure (FPGA, cRio) signals

    Hello

    I'm seeing repeated in my measurements values and trying to determine the cause

    I read a single analog channel from a module NI 9201. In order to eliminate the noise, I averaged several samples by using the ms and RMS measures VI (shown in "FPGA Code.png")

    An example of repeated values appear in the "comparison of Signals.png' for both the original signal and mean

    The sampling frequency of the NI 9201 module for a single channel is 500 kech. / s, which I also checked by measuring the sampling frequency (the code for this is also reflected in "FPGA Code.png")

    On the target of cRIO RT I record these values in a loop timed 500us using 1 MHz of the cRio clock

    For the ms and RMS measures VI, I tried several options, for example:
    -500 US measurement time, sample rate 500 kech. / s
    -450 US measurement time, sample rate 450 kech. / s
    -400 US measurement time, sample rate 400 kech. / s
    -US 300 measurement time, sample rate 300 kech. / s

    Each of them give measurements with repeat values to varying degrees, for both original and average signals

    Any suggestions?


  • LabVIEW with error FPGA cRIO

    When you try to run a VI that if interface with cRIO I get code error-63191. My cRIO is connected to my computer via an Ethernet cable, the cRIO and mobile LAN are the same IP address. The Project Explorer and MAX are able to detect the cRIO. Project Explorer is able to connect and to deploy.

    I tried to change the IP address in the 168.192.0.11 to 168.192.0.10 Project Explorer as the cRIO-9004 element is connected to the title of the first IP address, Project Manager (which seems to serve as an interface with the cRIO-9103 component) may be intellectual property conflicts. I end up getting a different-63040 error code.

    The first error screenshots are attacted and MAX and connection project manager

    Hello WheelchairDev,

    On this screenshot you just sent to the course, it seems that you do not have your project set up properly. You should have your project-> cRIO target-> cRio-> target FPGA chassis.

    If you want to see an example of this, of the LabVIEW startup window, select the FPGA project in the drop-down menu of targets to create a sample project.

    Once you change the layout, let me know if you have any other questions.

  • How to read the status of User1 DIP-switch with a cRIO FPGA chassis?

    How to read the State of the DIP switches on a FPGA cRio chassis?

    I work with a cRIO 9022... My idea is to put the system in "service" mode with USER1 switch to IT and communicate with the FPGA via the FPGA - GUI (VI) on the host computer instead via the RT module that is used in normal conditions.

    Any ideas? Unfortunately, I don't have an unused channel on the left... .and (as I know) cannot use the interface RS232 of FPGA.

    Many thanks in advance,

    Luke

    Hi, this is the correct information. You cannot read the FPGA of DIP-switch status. The only thing you could do is to use the function of Reading Switch.vi located under the range of functions-> real-> utilities RT time

    It's how you probably know side host RT and not the FPGA.

    Cordially Virginia

  • Encoder protocols

    I never realized there are so many serial encoder protocols until I was responsible for investigating making some encoder testbeds. Open protocols should not be a problem, but to service, repair and test encoders with closed protocols will take some work, if it can be done at all. Any suggestions? They do a 'universal Protocol Analyzer' for encoders?

    You will need to try to get the protocols tailored to each manufacturer. I know that Yaskawa publishes information on their protocol, even if it isn't a standard protocol

  • added module cRIO-generic

    Hello

    I - labview 2011,-LVFPGA in real time-, - NIRIO 4.0, cRIO - mdk 2.0 and cRIO module - support 4.0.1...

    I work in the construction of a new module of m... first of all, I want to control the slots on the frame... So, I run, software part of that
    application ==> http://zone.ni.com/devzone/cda/tut/p/id/7868
    and it works... I see the signals on my oscilloscope...

    The problem is that I couldn't find a way to add the generic module to my own FPGA project...

    I also study the sample application by giving this link ==> http://zone.ni.com/devzone/cda/tut/p/id/4539
    and you see it add the cRIO-generic module in embedded project.

    Here's my way

    * I m creating an empty project and add cRIO-9004 by > right click (Project) > New > target and devices > time real compactRIO > cRIO-9004
    * and then, good click target FPGA (cRIO-9103) > New > C Series Modules > new target or device > C Series Module

    but I couldn't see the module "generic"...

    What I m missing?

    I had the same problem. Arise in 2009, but not 2011. See this:

    http://forums.NI.com/T5/real-time-measurement-and/I-don-t-see-quot-cRIO-generic-quot-on-the-module-T...

    I added the line "cRIO_FavoriteBrand = generic ' in the ini file." He now appears less 2011.

  • Combine the cRIO 9076 and cRIO 9081

    I have two controllers time real FPGA: cRIO 9076 and cRIO 9081.  Due to not having the latest version of LabVIEW (2011), I am unable to use cRIO 9081.  CRIO 9076 not having only 4 slots for modules, I am using cRIO 9081 as a slave just to add more modules on its machines slot.  Will this work?  If so, how can I connect the cRIO 9081 to cRIO 9076. Any suggestion is appreciated.

    Hello ExcelX,

    Unfortunately, there is no meaningful way to interface with the 9081 without going through the correct versions of LabVIEW (at least 2011) and NOR-RIO (at least 4.0). It does not have windows, so you could theoretically it boots into Windows and plug a monitor on it, but you wouldn't be able to run any code on it.

    You can download the demo version of LabVIEW 2011 and use it with your 9081 for thirty days. But I recommend you just upgrade to LabVIEW 2011 - the 9081 is a powerful (and expensive) CompactRIO.

  • Representation of State-space Discrete in FPGA

    Hi all

    My goal is to simulate a State-space model is the FPGA cRIO (order to use an observer).

    I am currently trying the simulate on my computer without using the VI state space discrete Control Design and Simulation Toolbox (since there is no model of State-space for the FPGA VI). However my representation of the discrete state-space model does not work.

    It is under a continuous state space model:

    Then I got the model discretized (using the zero-order-hold and t = 0.01 s):

    Here are the State-space discretized model I designed (to develop a similar model in the FPGA):

    This is the VI space of discrete states that I use to compare the results:

    The chart plot the State X 1, which is growing indefinitely. However, it should look like a first order, as you can see:

    I don't understand why the State X 1 progresses like this, I know I'm missing something (saturation of integration?).

    Thanks in advance

    Kind regards!

    PS: Does anyone know if application other than the PID controller is feasible in the FPGA cRIO? I also have to wonder about the inversion of the matrix if I want to use the Kalman gain in my observer.

    PS2: I apologize for my disorganized/not clear Labview files, I start with him.

    Hello

    I think that the problem can be caused by errors in your matrices A and B of rounding.  Have you tried to make her show values more accurately?

    MATLAB calculates these values as: A = [0.995, 0.009925; 0 0.99], B = [2.488e - 5; 0.004975]

    Kind regards

    Ian

  • Laser digital lock with Labview FPGA?

    Hello

    Sorry to bother if you are not interested in this issue of digital signal processing. We are looking for a possible digital solutions to our problem locked frequency cavity closed-loop laser (see attached PDF file for more details).  The goal is to flatten the PZTs transfer function (cancel the resonances and anti-resonances and their phase shift matching) in the frequency domain, in addition to the normal PID control.  Input/output necessary voltage signals are small (we have our own amplifiers high power for the PZTs), and their bandwidth must be at least of 50 kHz (100 kHz would be optimal).

    Among various OR hardware/software (DSP, FPGA, cRIO etc.), would anyone recommend a cost-effective solution for rapid prototyping?

    Thank you!

    I would like to look at the FPGA PXI cards nor 7854r.  I rate of 750 kHz, 1 MHz AO.  According to the involved treatment, you might expect between 200 and 750 kHz closed control loop.  If the treatment is very intense, it's probably something less than 200 kHz.

    That said, the key to these performance levels is not trivial and great care and attention to detail must be used in the coding of the FPGA.

    Good luck

  • Start by cRIO

    Hello

    Applications based on the what is the cheapest way to start programming of FPGA cRIO? I am interested in learning to develop a FPGA and cRIO but cannot afford the cRIO, is there an inexpensive way to simulate these (I think that even the drivers in real time can be expensive)

    I found this kit eval for RIO, but I don't know if that's what I need to start learning about LabVIEW cRIO/FPGA development?

    http://sine.NI.com/NIPs/CDs/view/p/lang/en/NID/205722

    Thank you very much!

    Yes - I agree with GerdW that the myRIO is a great way to get started with cRIO & RT/FPGA programming. It is very easy to install and use.

    I recently used one for a personal project - creation of a giant version of Tetris! (https://decibel.ni.com/content/docs/DOC-35435)

    I can also recommend the eval kit - it comes with a single card RIO Board addon that contains many useful things to begin with RT/FPGA programming (an LCD display, input/output analog that are related, some buttons etc.). I currently have one on my desk at work that we do things recently with LCD screens. They also CAN embedded (car for example) so if you are interested in doing anything with that then I don't think that you can do with the myRIO.

    If you arrive the myRIO cost low enough (because you are not a student-, but it should be talk NOR anyway) then the eval kit is a bit more representative of what it's like using a cRIO and you can go further with it without needing any additional hardware.

  • target types are not cRIO

    Hey Gang,

    I'm trying to get a new cRIO flight for a client project.  I have LV 2010 and 2012 on my computer.  I've got modules RT in both.  I made a project of RT/FPGA cRIO since more than a year.

    The cRIO shows 'execution' in MAX.  Some modules are visible in the remote Manager application.  My gut tells me that the cRIO is correct.

    When I try to create a project of RT in 2012, RIO Compact does not appear in the list of the types of targets, so I can't select the cRIO chassis.  Selection by IP address is 'something' in a project file, but no options appear.

    I tried the same thing in LV2010, and everything goes as planned, until I try to DL on the RT controller.  It returns an error, something like: 'Unexpected Version of RT OS' probably a newer version.

    According to me, I'm missing some software, or it is not connected to LV2012.  NOR-RIO 4.0 is installed on my computer.  I can see through the tree of the max software.

    I wasn't expecting this part of the project to take even a day to start, so I can't wait to help.  I'll appreciate any ideas.

    Thank you!

    Roger

    Hi RogerMont,

    You will need OR RIO 2012:

    http://Joule.NI.com/nidu/CDs/view/p/ID/2969/lang/en

    DylanC

Maybe you are looking for