Exactly how memory works in Labview Fpga

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  Hey phg,.

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• Use of FIFO memory on two areas of clock (Labview FPGA) block

  Greetings!

  I'm developing an application on the FPGA of the vector signal OR 5644R
  transmitter/receiver. I have two loops single-cycle timed: a 40 MHz making a convolution
  and writing a FIFO memory block and the second at 120 MHz (sample clock)
  who reads from block FIFO memory and uses the following values
  interpolation...

  Under what circumstances is it permissible to use a FIFO memory block to transfer

  values of a loop from 40 MHz to a loop of 120 MHz (sample clock)?

  The reason I ask the question, it is that the compilation of my code repeatedly of not
  reported the error below:

  ERROR: HDLCompiler:69 - "/ opt/apps/NIFPGA/jobs/J9k7Gwc_WXxzSVD/Interface.vhd" line 193: is not declared.

  I share for everyone's reference, screenshots of my code which is an extension of

  sample 'Project streaming VST' given in NI5644R. A brief description of attachments is

  given below...

  1. "Top_level_FPGA_part1_modification.png": in a loop SCTL 120 MHz, a sub - vi bed FPGA

  go a block FIFO memory... In fact, the reading is actually made when entry

  "read_stream" is activated... (see details in read_from_fifo_true_case.png)

  2. "Top_level_FPGA_part2_modification.png": a 40 MHz SCTL, wherein is a subvi FPGA

  called to write the output of convolution to block FIFO memory.

  3. "target_respone_fpga_block_FIFO_modification.png": an output of a convolution filter is

  written in block FIFO memory each time that the convolution output is available...

  'ReadBlockFIFO' VI (circled in Top_level_FPGA_part1) is invoked in a 120 MHz SCTL.

  4. "read_from_fifo_false_case.png": when the input "read_stream' of this vi is false,

  data transfer memory FIFO of block to a different FIFO ('generation filter") takes

  place.

  5. "read_from_fifo_true_case.png": when the "read_stream' is set to true, the data is read in

  'Filter generation' FIFO and spent on the chain of later interpolation to the

  120 MHz SCTL...

  I hope that the attachments give enough clarity to what I'm doing... If we need

  For more information, do not hesitate to ask...

  Kind regards

  S. Raja Kumar

  Greetings!

  I think I understand the problem... The error probably occurs because a DMA FIFO

  (FPGA host) is playing at 40 MHz, and it is checked for the number of items in a loop

  120 MHz... It is not captured by the "pre-processing" by the labview FPGA, but by the Xilinx

  compilation phase synthesis tool.

  A lesson I share, is that if you observe this kind of problem, watch if there is incompatibility

  in the areas of the clock to access a FIFO...

  Kind regards

  S. Raja Kumar

• How to import codes Verilog in LabVIEW FPGA?

  I tried to import the Verilog code by instantiating followed education in http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3.

  but I can still see some errors when compiling the file VI.

  Test file simple Verilog is as follows:

  ==============================

  module andtwobits (xx, yy and zz);

  input xx, yy;
  output reg zz;

  always start @(xx,yy)
  ZZ<= xx="" &="">
  end
  endmodule

  ==============================

  and after you follow the above link, we have created the instantiation as file

  ==============================================

  Library ieee;
  use ieee.std_logic_1164.all;

  mainVHDL of the entity is
  port)
  xxin: in std_logic_vector;
  yyin: in std_logic_vector;
  zzout: out std_logic_vector
  );
  end mainVHDL;

  architecture mainVHDL1 of mainVHDL is

  COMPONENT andtwobits PORT)
  ZZ: out std_logic_vector;
  XX: in std_logic_vector;
  YY: in std_logic_vector);
  END COMPONENT;

  Start

  ALU: andtwobits port map)
  ZZ-online zzout,
  XX-online xxin,
  YY-online yyin);

  end mainVHDL1;

  ==============================================

  Sometimes, we observe the following error when we put the flag on the output port.

  ERROR: ConstraintSystem:58 - constraint

  TNM_ChinchIrq_IpIrq_ms; > [Puma20Top.ucf (890)]: INST
  "* ChinchLvFpgaIrq * bIpIrq_ms *" does not correspond to design objects.
  ERROR: ConstraintSystem:58 - constraint
  TNM_ChinchIrq_IpIrq; > [Puma20Top.ucf (891)]: INST ' * ChinchLvFpgaIrq * bIpIrq. "
  does not match design objects.

  and Interestingly, if we remove the indicator from the port of exit, he sucessfully compile on the LabVIEW FPGA.

  Could you take a look at and please help me import Verilog to LabVIEW FPGA?

  I followed the basic steps of the instantiation on the link above, but still it will not work.

  Please find the attachment for all files.

  -andtwobits.v: original file from Verilog

  -andtwobits.ngc: file UCS

  -andtwobits.vhd: VHD file after translating a simulation model

  -mainVHDL.vhd: master of the instantiation

  Since there is no sample file for Verilog (VHDL file, there but not for Verilog), it's a little difficult to do simple execution on LabVIEW FPGA, even for examples.

  Thank you very much for your support, and I'm looking forward to seeing all your help/answer as soon as possible.

  Records,

  The best instructions we have for integration Verilog IP in LabVIEW FPGA can be found here: using the Verilog Modules in a component-level design. My suspicion is that you did not uncheck the option 'add the IO buffers' in the Xilinx ISE-specific Options parameter when running XST (see page 8 of the .pdf)