Example rate vs clock rate cRIO

I try to get my head around the difference in sample rate vs clock rate in the cRIO so I can explain it correctly my engineers in optics.

I have a FPGA code that is just the Basic with e/s example.  Modules 1, 2 and 3 are NOR-9201 with a sampling frequency of 2uSecs.  The FPGA runs at 40 MHz or 25nSec/Cycle.  Read in the documentation of the loop While takes at least 3 clock cycles.  Estimate that other functions of the loop take about 7 clock cycles, the loop should run in 250nSec.

This is faster that the 9201 - can enjoy.

What does the FPGA?  He expects the sample at the end?  Takes the value of the previous sample?  Do we get a partial sample?

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Paul_Knight_Lockheed_Martin wrote:

He expects the sample at the end?

Yes - the loop runs in reality more slowly - he will meet at the level of the I/O node to the end of the sampling - time which is the sampling rate of any module is in the loop. For example, some modules analog high-resolution have read very slow time (like 52ms) then the loop will run at a rate of around 52ms (according to any other code you got in there).

If you have the e/s high-speed digital, you almost definitely want to put it in a different loop at any analogue I/O so it is not slowing down your loop.

I think that some modules are able to run in a single-cycle timed loop - in this case, the module will run in a single clock beat (for example 40 Mhz).

Tags: NI Software

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