External clock as a time base (NI PCI-6122)

I use the PCI-6122 card and you want to provide an external clock very specific (preferably 10 MHz) as a time base. I tried to connect my external clock signal to PFI - 8 and then internally of PFI-8 road to the RTSI-7, but it did not work. I use only one card, and have therefore no beeing rtsi cable installed.

Can you help me set up the card to use my external clock?

Thank you for your help. It seems that there is no way around and I have to 'spend' an additional signal generator (locked my 10 MHz reference) to provide a sample clock, locked in my experience.

Tags: NI Hardware

Similar Questions

  • By dividing the time base clock sample by N, we're the first sample on pulse 1 or pulse N?

    I use an external source for the time base a task of analog input sample clock. I'm dividing down by 100 to get my sample clock. Is could someone please tell me if my first sample clock pulse will be generated on the first impulse of the source of the base of external time, or about the 100th?

    I use a M Series device, but can't see a time diagram in the manual that answers my question.

    Thank you.

    CASE NO.

    CERTIFICATION AUTHORITIES,

    I don't think it's possible to use the sample clock of 3 kHz on the fast map as the time base clock sample on the slow map and get the first sample to align.  The fast card can enjoy on each pulse signal 3 kHz, while the slow card will have to meet the requirement of the initial delay before he can deliver a sample clock.  If you turn this initial delay a minimum of two ticks of the time base, the slow card eventually picking around the edges of the clock 2, 102, 202, etc..  You can set the initial delay for 100, which means that the slow card would taste on the edges, 100, 200, 300... but you wouldn't get a card reading slow on the first edge of your sample clock.

    Hope that helps,

    Dan

  • cDAQ HAVE task using external clock

    Hi, I am trying to use a clock signal on a line of PFI in order to generate a clock, but at a lower rate, for a task to HAVE.  I run into many issues that I can't explain.

    I have a cDAQ-9172 with an entrance module analog (9225) in the Groove 3 and a digital input module (9411 - 2 MHz DI) into the slot 6 (where the PFI lines are accessible).  I want to use an external signal on et0/PFI0 to act as the clock for an analog input on the 9225 task.  This signal comes from the cDAQ anothr chassis and is too fast for the task to HAVE it, so I intend to use the time base entrance and the divider to clock (as shown on page 31 of the cDAQ-9172 manual).  See picture attached for a graphical representation of my problem.

    If I have the wiring from the signal "/ cDAQ2Mod6/PFI0" in the DAQmx timing VI, get the error 200414 saying that "required sample clock source is not valid."  It is strange because it is listed as "Direct route" in Max (the VI of polymorphic DAQmx Timing is configured as 'Sample clock') Q: why this route is not suitable for the task?

    If I use DAQmx Timing property node and change the Source 'Sample clock Timebase' to ' / cDAQ2Mod6/PFI0 ", the task starts without error, but the separation seems to be forced to 256.  If I try to change the properties of the separation of the time base, I get error-201100.  Try to change the 'sample clock rate"doesn't have any impact on the task and the remains of divider"256 ".  Q: why the 'Programmable clock divider"locked to 256 when using the PFI line or can you just not program directly?

    I came across another error is the minimum speed on the PFI line.  If I have the wiring (for the SamplClock Timebase) lower at 1 MHz, LabVIEW returns error-200077.  The error message indicates that the minimum value is 1 MHz.  9172 manual shows the clock 100 kHz is an option for the time base, certainly less than 1 MHz.  Q: What are the limits of upper and lower frequency for a clock signal on the line PFI for the ' Timebase AI/SampleClock "?

    I looked on the site and in the DAQmx documentation for further explanation, but I have been unable to explain these strange behaviors.  What are the barriers to entry of Timebase PFI and the time base "Programmable clock divider" preventing me to reach my goal here?  If I can't do it directly, can I use the PFIn signal to feed an internal counter (to act as the clock divider) which could then generate the clock WAS at the rate I want?  This method would allow me to perform a division arbitrary clock (unlike the ' 256', which seems to be forced on the PFI as a Timebase SampleClock.)

    Finally, something seems odd that I can make an acquisition to 10Sa/s max but when I start a task using an internal timers of the cDAQ9172 and ask a 10Sa/s rate, the task really gives me a rate of 1612.9 sample/s while using the 12.8 MHz clock and a divider 7936 timebase.  Q: Why can't the task to 10Sa/s?

    I use DAQmx 9.7.0 and LV2012 SP1 (and I tried with 9.7.5 but I got the same results)

    Thank you

    Olivier

    I got additional help Friday in another engineer at NEITHER and the solution to my original problem is actually very simple to get the clock from an external source path:

    The idea of picking a PFI line for the basis of 'time' and the 'Programmable clock divider"(in fact, DAQmx calculate this number based on"HAVE sample time clock"and"Sample clock HAVE") works by using the node property below:

    (SampleClock.Source cannot be resolved until the task is clerks/reserved, but the default option seems to be the time base that works well in this case.)

    The question that I described earlier with the 9225 comes the module properties and the fact that it is a "Module of Sigma - Delta".  That the module usually generates its own time of 12.8 MHz base clock (page 14 of the document 9225 # 374707) and the clock divisor is much less possible values than the other modules (must be a multiple of 256). It may use a different time basis from a PFI line, but it must be between 1 MHz and 13.15 MHz.

    So a main clock between two chassis and tasks running at different rates of sharing should be easy and simple with most of the modules.  With AI modules with Sigma-Delta converters add additional limitations and the master clock for the time base frequency must be selected to accommodate these module as well.

    Another good news is that the Simulator seems to bear all these details and DAQmx (9.7.0 in my case) generates the same errors when you use a simulated chassis if you use real body.  Play well!

  • GPS sync and external clock

    Hello everyone,

    my task is to synchronize my PXI system to the time base GPS and after using an atomic clock (10 MHz output signal) as well as external CLK in. after the first synchronization of the GPS. the GPS signal is no longer available, however very important as the base unit of time not significantly drift. For the material there is a PXI chassis with 6682H module for GPS reception and 5622/5603-5653 combination for the acquisition of measurement data available.

    I thought since I'm fairly new to Labview and PXI system, it would be nice if someone could give me some feedback on the solution and help solve the problems that I have.

    The idea would be to have atomic clock connected to all CLK INs the PXI at all times. For GPS sync I would use the "Set time reference niSync' function first set the clock of Council to the GPS. After the free trial (the device is not moved during the GPS synchronization) I would like to stop using the GPS.

    After the external atomic clock. should also be used to calculate the frequency increases and the determination of the relative time. I suppose that if I back the reference to free running time, it would still use the last increments of calculated frequency derived from GPS?

    Is there another solution to address both reference to PPS? Problem is, I only have a 10 MHz signal available.

    Thanks a lot for any help

    Hello.

    When the PXI-6682 tries to synchronize to a source (GPS, 1588, PPS), she is a great fit for its time base, to eliminate the first offset from the source and then made small developed to the clock, the timekeeper, to keep in sync with the source of the conduct.

    In this case, you have an atomic source at 10 MHz that you trust, so you do not want/need small adjustments, you want to only make the initial adjustment of wholesale and then just run based on the clock of 10 MHz supplied.

    Is there a way to make the PXI-6682 to do this.  You will need to configure it to assume that PXI_CLK10 is good and no adjustment is necessary. There is no call to the Sync API OR standard to do this, you need to get the VI that configures the jury to do this in the .llb used to clock discipline (in which the PXI-6682 also doesn't make small adjustments based on his time, but guess PXI_Clk10 is 'good').

    You can get the .llb from here: http://joule.ni.com/nidu/cds/view/p/id/2318/lang/en

    The VI you need is mdevClkDisc.llb\_clkDisc_niSync_advancedAttribute_set_bool.vi

    Together the "attribute of niSync" entry "Clk10 disciplining activated ' and the 'value' of coming true, as shown in the picture as an attachment.  The time reference offset must be<10ns and="" constant. ="" give="" that="" a="" try="" and="" let="" us="" know="" how="" it="">

    Note that once you do this, the PXI-6682 will be able to make adjustments to his timekeeper. It will work exclusively on the 10 supplied MHz reference clock. Therefore, if the clock of 10 MHz in fact derive from GPS, there is nothing that the 6682 can do about it.  If you fall into this situation, one thing you can do is set at a time reference to free running, set the time to something that is off by saying that 60 seconds, and then set the time reference to the GPS.  That should put it back on the rails.

    I hope this helps.

    Alejandro

  • Increase in the rate of sampling with external clock

    Hi all

    I have hardware DAQ-SMU-6361 and SMU-8360 controller in an express chassis SMU-1071. My 6361 maximum sampling frequency is 2 MECH. / s. But I want to use my daq with higher sampling rates. After going through the various positions, I decided for two options to increase my sampling rate. You must connect a 5 MHz signal generator to use as an external clock. Another is to use the timer to synchronize PXI Chassis

    My question is

    (1) what is the limit to the frequency that we can use as external clock for data acquisition? Which parameter is limiting the performance of the ADC, if we use the higher clock frequency signal?

    (2) I also learned about an option called 'base time in PXI Express chassis'. can I use this option? Someone please give me a link to a good tutorial on the basis of time in a single PXI Express chassis?

    (3) SMU-1071 chasis, 100 MHz differential clock. Is it possible to use it as a clock to my DAQ 6361 signal?

    Concerning

    Vaidhin.

    HI Vaidhin,

    The article mentions the background basket clock as a possible means for synchronization, but this is accomplished using it as a phase reference clock - align the oscillators on board your hardware DAQ which are then distributed down to produce the sample clock.  You may not use background basket clock or time base on board directly as a sample clock (on the one hand, these signals is much too fast).

    Measuring 1 MHz with a DAQ hardware 2 MHz could not give you what you expect.  You will get 2 points per period of your entry - it's just at the limit to avoid aliasing of your signal and of course do not a good characterization of the shape of your signal.  You might be able to push the card in slightly beyond 2 MHz but not significantly enough to make a huge difference.  You are right that if you have sounds at higher frequencies could be an alias down in your signal.  Any noise above ~1.7 MHz will begin to be eased by a bandwidth limited the 6163 (there is a chart in the specifications , showing the bandwidth).  If you have between 1 MHz (signal) and ~1.7 MHz noise, you might look into an external filter, but again you are always sampling very slowly to be able to characterize the shape of the signal.

    The next steps to the top (in terms of sampling frequency) would be as follows:

    4 MHz: SMU-6124

    10 MHz: PXI-6115

    There are currently no products that use the same DAQmx driver who can enjoy beyond 10 MHz, but NEITHER there also a range of scanners that you may enjoy a lot faster.  If you are interested in sampling up to 100 MHz, you may consider looking in the SMU-5122- there are also faster scanners available, but these are probably not necessary for your application.

    Best regards

  • activate the external clock

    Alrighty, I'm a total noob to LabView and others. I'm at the point where I don't even know if I know is relevant, so forgive if I give too much information and probably not enough.

    I've got:

    cDAQ-9174 chassis

    9422 module into the connector #2

    This 9422 module will be connected to a meter that will send a square wave. What I need is the frequency of the square wave. Problem is, I don't have any idea how to get it.

    I open a new .vi and use the DAQassist. From there I select entry counter and then I tried the frequencies and Edge Count.

    At the end of the day, either it usually gets me the following error message:

    Error-200284 occurred to...

    Possible reasons:
    Some or all of the requested samples are not yet acquired.

    I guess that one I did most of the research is the counting of edge. It is continuous samples because I need to monitor the flow rate at the time rather than only to count the edges of time 0 until I stop the VI. So there are different ways to treat this error include changing the timeout value, something to do with 'samples to read' and 'sample rate', and then that it seems to me that I have to do: since the buffered continuous one requires an external clock, which is specified in the tab "Advanced Timing" of the menu properties DAQassist I have a lot of things to choose from. It seems/I/SampleClock or/ao/SampleClock is the thing to choose, but then several Web pages continue to say to make sure that the external clock is actually "run", or any word in this sense. So I tell myself, my external clock isn't doing anything and that's why reading isn't acquire samples. But really, I'm just lost. Then...

    Question 1:

    Is what I'm working on the best/right way to go about doing this?

    Question 2:

    How can ensure me that this external clock done everything what it is supposed to do so that I can get samples still for edge counting?

    Well, my ignorance is exposed, please fire away. I have attached the .vi, although I don't think it will tell you anything other than I know how to click the mouse button when running LabView.

    County Board is time since you don't have a sample clock.  You can provide one from many sources, but in your case I suggest sticking to a task of frequency measurement I won't go into it now.

    The frequency could be time for a number of possible reasons:

    1. the external signal is not connected to the right Terminal (the default IS terminal your meter chosen if you not him have not overridden with a property DAQmx node which is not possible in the DAQ Assistant).  For the 9422:

    2. the signal may be connected to the right Terminal, but perhaps, it does not meet the specifications of the 9422 to be detected)<5V low,="" 11-60v="" high).=""  you="" can="" verify="" whether="" or="" not="" the="" signal="" is="" being="" detected="" using="" a="" test="" panel="" (counter="" edge="" counting="" to="" determine="" if="" the="" signal="" is="" present)="" in="" measurement="" and="" automation="">

    3 tasks of frequency are sampled off the input signal - so if the input signal does not switch when you start the program or if there is a long break (longer), you will receive the time-out error when the reading function blocks for more than your specified time-out.  You should be able to just 'manage' the time-out error so that if it happens you can report a frequency of 0, ignore the error and try to read it again.  There are also other approaches such as using events DAQmx or samples available to read to vote, but none of them are available through the DAQ Assistant (the idea is that you avoid making DAQmx Read blocking call until you know there are samples to read).

    Configure a task of frequency is a better option for you, because it will give more precise (although you can set a task of County of edge to behave similarly to a frequency measurement task, this is trickier and you can also use the DAQ assistant).  You can start out by setting 1 sample (on request) for the synchronization mode - this will return a single sample as soon as it is available.  If you put the DAQ Assistant, in a loop, you will get a new sample at each iteration (or if your input signal goes, the samples will stop coming in and you'll get time-out errors instead).  The downside is that you will not receive a sample on each side - entry task is reset by software and during this downtime between the samples will take no new data.  This should be good for the case of the use you described (the frequency of a continuous square wave periodically monitoring).

    So, make sure that the external signal conforms to the specifications of the 9422, and it is connected to the correct terminal (the PFI line which is equivalent to the DOOR of your meter by default).  If your external signal is less than 0.2 Hz (1 sample every 5 seconds) you will need to move away from the DAQ assistant, as it seems that it is not possible to set the timeout of read using the DAQ Assistant (surprisingly).  You might want to look in the API of DAQmx lower level anyway - here is a simple example to help you get started in the affirmative.  It's really not too complicated and once you get used to it will be less heavy than using the DAQ Assistant.

    Best regards

  • To use the external clock for SCTL myRIO

    Hi people,

    I'm trying to find a way to get a 2.5 PSM 16-bit ADC, TI ADS1602, to send data to the device myRIO. Ideally, I'd like to bit Records at 40 MHz in order to obtain the benefit of the PSM full 2.5. I know that I can create an 80 MHz SCTL on the FPGA to create a clock of 40 MHz, but when I checked the clock on an oscilloscope signal, it was obviously greatly degraded by bunch speed limits, so he looked more like a sine wave to a square wave. I doubt it would work for use as a clock signal to drive the ADC since ADC specifications say that eligible jitter is around 100ps.

    I can use an external oscillator to drive the ADC, but then I have to find a way to sync the clock with clock FPGA 40 MHz. is there any kind of PLL structure that would allow me to sync the clock FPGA myRIO to an external clock? Is there a way to do a loop simple timed cycle driven by an external clock? Or if I was able to customize the FPGA personality to accept a SPI signal up to 40 MHz (ten times her supported limit...), he would be allowed to use an FPGA to ~ 160 MHz and tell him to taste the SPI line each loop and proceed from there?

    Thank you!

    Hi 3.14159... ,

    The myRIO doesn't have the ability to import a clock to use on the FPGA block diagram for clock loops timed cycle unique (SCTLs). The sbRIO-9651 new coming out week OR (not shipping yet) is the only sbRIO who has the ability to import an external clock in LabVIEW. Many of our products FlexRIO also have this ability.

    Like you we have it, you can taste the signal at twice the frequency (or maybe more) to and wait an edge trigger to run a certain element of logic. "" "If you open the example Finder and navigate to hardware input and output" R series "FPGA Fundamentals ' triggers and guard dog" trigger detection, this gives a simple example to do this. Once again, since you are eager to taste 10 times the frequency of support, all bets are off, but it may be worth trying.

  • divided time base

    In the simultaneous measurement with AI and AO, I used SMU-6124, that supports the time base of 80 MHz clock.

    I was told that I can use 80 M/n (integer) as a sampling in SMU-6124.

    In order to obtain n is integer, I limited my settings for 2 to 5 common factors.

    But, why the actual sampling frequency is different from the sampling frequency of entry, 1.6 MHz (n = 50).

    Real rates are 1.67E + 6 (analog input) and 1.54E + 6 (analog output).

    What is the problem for this problem?

    Any other consideration in its sampling frequency?

    labmaster.

    Hi labmaster,.

    Looks like you're on track - to answer your questions:

    0) meter tasks can use the time base of 80 MHz (20 MHz and 100 kHz are also available).  So the frequencies available, you can generate using the meter is 80 MHz/N, where N is an integer (between 4 and 2 ^ 32).  You are still limited to the average fracture, but you would work with a higher time base so you could reach the frequencies that you couldn't otherwise (for example 1.6 MHz).

    (1) you can check the actual sampling frequency of the counter by using the following property node:

    (2) you can run GOT it, AO and two counters at the same time in separate tasks - I'd start, AO and Ctr2 before Ctr1 so that all tasks starts at the same time.  If you started Ctr1 first, then the clock will then perform tasks would begin at different times (software-based) unless you use a trigger to start.

    I'm glad to hear that this has been helpful to you, I hope all is well and good luck to you with your application!

    -John

  • Period with external clock measurement

    Hello

    I have the USB-6210 and I'm using Labview 8.0.

    I use the 6210 for period measurement of a signal. I have another card (not OR) I want to synchronize with the 6210. The other card has a clock of 10 MHz with a TTL output.

    I am trying to use the 10 MHz TTL of the other card as an external clock for my measurements (this would essentially be synchronize both). The measure of the time does not support external clocks. I can't make the edges of the county if not work. Any suggestions? Is it possible to sync the 2 cards? If this is not the case, what are my options?

    Thank you very much

    Eyal

    Hi Eyal,

    How did you get your task configured?  It should look like this:

    Best regards

  • Reading and samples the sampling frequency using a fast external clock

    Hello

    I use an NI USB-6212 box to launch a search engine for combustion. I have a pressure sensor in the head and a wheel on the crankshaft. I use the beats A Quad channel of the rotary encoder as a sample external to the pressure with the sample clock. The idea is that I want almost the same number of points in each trace of pressure so that it is easy to average together. I seem to be able to do this at low speed, but I'm having issues at high speed.

    Can someone tell me what I should have my sampling rate and samples to read together and how it effects my sampling when using an external clock? Samples per channel will affect the size of buffer and that matters? When I was high (10-100 kHz and about 1/10 * rate for samples to read) it barely read but as I put the lowest and lowest he read faster. Play with the settings a bit seem to affect how well it samples at different speeds. The engine is running at 3600 rpm and my encoder puts out 2500 pulses per turn on one channel, I'm looking at a frequency of 150 kHz effective sampling. However I didn't sample program with the engine operating at full throttle. I hung on the output of the encoder up to a scope and reads very well.

    Are there opportunities the filter counter that I see in the manual of 621 x is enabled inadvertently?

    Thank you

    Xander

    Xander18,

    I suggest you move your screws initialization outside the while loop, as well as your narrow DAQmx VI.  On my side, it looks like a new task is performed for each loop, which takes time.  That a try and let me know how it goes.

  • 'Resources in use' error during the acquisition of the analog data on AI0 with external clock on PFI0 and beginning of slope trigger analog on AI1

    Hello

    I use the card PCI-6111.

    I am trying to acquire analog data on channels dev1/ai0 ai1/dev1 using pulses of external clock connected to the PFI0 channel. I also want to trigger the acquisition, when the channel dev1/ai1 signal reaches certain level. I send a triangle wave channel dev1/ai1, and I need the data only for the front.

    I have configured the task in the following ways:

    However, I get the error-89137 after function DAQmx Start Task:

    Specified route can not be satisfied, because it requires resources that are currently in use by another route.

    Source device: Dev1
    Terminal of source: PFI0InputLockOut
    Target unit: Dev1
    Destination terminal: AnalogComparisonEvent

    Resources in use by
    Task name: _unnamedTask
    Source device: Dev1
    Terminal of source: PFI0
    Target unit: Dev1
    Destination terminal: AI/SampleClock

    Task name: _unnamedTask

    If I change the internal clock external clock - switch works. If I pull the trigger, the external clock works, too. But these two tasks do not work together.

    Help? Advice? Thank you!

  • How to read multiple channels based on the external clock

    Hello

    Normal 0 false false false MicrosoftInternetExplorer4 / * Style Definitions * / table. MsoNormalTable {mso-style-name: "Table Normal" "; mso-knew-rowband-size: 0; mso-knew-colband-size: 0; mso-style - noshow:yes; mso-style-parent:" ";" mso-padding-alt: 0 to 5.4pt 0 to 5.4pt; mso-para-margin: 0; mso-para-margin-bottom: .0001pt; mso-pagination: widow-orphan; do-size: 10.0pt; do-family: "Times New Roman"; mso-ansi-language: #0400; mso-fareast-language: #0400; mso-bidi-language: #0400 ;} "}

    I use 6254 multifunction for playback of tension with VC ++ 6 as the development tool.

    Based on the documentation NOR I created tasks like this.

    DAQmxCreateTask (_T ("Voltagetask"), & taskHandle);

    DAQmxCreateAIVoltageChan(taskHandle,sChannels,,DAQmx_Val_NRSE,0,10,DAQmx_Val_Volts,);

    DAQmxCfgDigEdgeStartTrig (taskHandle, "PFI2", DAQmx_Val_Rising);

    DAQmxCfgSampClkTiming(taskHandle,"PFI2",303000,DAQmx_Val_Falling,DAQmx_Val_FiniteSamps,nSamples);

    DAQmxStartTask (taskHandle);

    After the generation of clock finished thanks to the DAQmxReadAnalogF64 function, I tried to read samples of each channel.

    DAQmxReadAnalogF64 (taskHandle, DAQmx_Val_Auto, 10, DAQmx_Val_GroupByScanNumber, read, m_nStates & sampsPerChanRead, NULL);

    Total number of samples (nSamples) available in the buffer when the task is created with a single channel and several channels are still to come as even. In several modes of channel returns total sample by channel, which is equal to the total number of samples divided by the number of channels at once.

    For example, if a total number of clock 8000

    With single channel, it reads all the 8000 samples (m_nStates = 8000, sampsPerChanRead = 8000)

    When two tracks he read 4000 samples per channel and so on. (m_nStates = 8000, sampsPerChanRead = 4000)

    If any body know, on every clock how to take samples of all of the configured channels.

    Thanks in advance,

    Renjith.

    Renjith,

    Please note that the behavior, I explained is in line with the provisions should only if you use your clock as I convert clock. You can find information about the different types of synchronization of the analog inputs using NOR-DAQmx; the element to search for is "clocks".

    Since you do not set the clock to convert MY (should be DAQmxSetAIConvSrc()), the fact that I mentioned above is only informative for you, but does not apply to your question.  Sorry for responding too quickly without looking in your code between quotes...

    In order to answer your question, we take a look at the approach to programming DAQmx:

    If you configure your task to be "finished", the task will stop running if the number of samples per channel is acquired. In the case of an external clock (not configured as I convert clock), served it in the sampling interval. The sample clock will automatically receive a sample for all channels with a single clock pulse. From this point of view, the installation program you have in your program seems correct.

    If you do not get the number of samples that await, the fault must be somewhere in your playback function. Do you get any error messages?

    DAQmxReadAnalogF64 (taskHandle, DAQmx_Val_Auto, 10, DAQmx_Val_GroupByScanNumber, read, m_nStates & sampsPerChanRead, NULL)

    If you set m_nStates set to 8000, it's here. You say the Read function to retrieve 8000 samples. None. So if you have two channels, DAQmx acquires 2 x 8000 samples, but read you only 8000 samples... Please change m_nStates to

    m_nStates = #channels x #samples by channel

    This should solve your problem.

    hope this helps,

    Norbert

  • HSDIO 6556 loses the lock on the external clock

    Hello

    I'm encountring a strange problem. I use my 6556 HSDIO to generate some model using and external clock (around 20 MHz and 50 ohms impedance). This clock is provided by an MCU and the entire application does not work well. However, when I tried to cool the MCU (up to-10 °) the HSDIO loses the lock and tries to re - lock again (the Red turned led active). When this happens, I can see a new phase shift between the data generated and the external clock, within the scope that is fatal for my application. L ' other, I inspected the data generated looking for a glitch or gigue appearing at low temperatures... Notice anything special... I tried to heat the MCU upward at 100 °, HSDIO does not lock...

    What can I do? 6556 HSDIO is apparently too sensitive...

    Mar1

    Hi Mar1,

    Datasheet public for the chip used in the States of SMU - overclocking 6556 a typical tolerance of jitter of 20 000 ppm, with minimum of 5,000 ppm. For a 20 MHz clock, this corresponds to 1 ns of jitter typical and 250 ps in the worst case. That being said, we cannot guarantee the specifications that are not included in the specifications NEITHER SMU-6555/6556 document because it is not updated with the production trial.

    Best regards

  • external clock or wave pulse or sinusodial?

    Hello

    I'll plug an external clock to 6711 map source. But I wonder if the source should be trains of pulses (wave squre) or it might be vague sinusodial. When we say the frequency of the clock, it means the occurrence of the rising or falling on board but not the pulse, right? And what is the range of voltage for the clock signal?

    Hi dragondriver

    The external clock should be a pulse train, not a sine wave.

    When we talk about frequency, as you said that it: the appearance of rising or falling edges within a period determined.

    Voltage range must be from 0 to 5V.

    Concerning

  • FPGA and external clock Source

    By using a PXI-7854R, is it possible to run a process on an external clock source? As far as I know, you could potentially bringing the external clock to one of the triggering RTSI lines. Is this correct? Is it possible to route through one of the connectors on the PXI-7854R? If this isn't the case, I also have a PXI-6229. Can the external clock be routed to the RTSI through the PXI-6229 and then line for the PXI-7854R to run the process?

    Hello

    Unfortunately not, as noted hereand here. The best solution is just the external clock with DIO on a structure of case to door. While this will not have any type of phase synchronization and you may miss the clock cycles depending on how long and how fast your external clock is running (not really an option). I hope that answers your question.

Maybe you are looking for