FPGA Butterworth filter - why conversions to decimal fixed?

I was looking through the screw FPGA Butterworth filter Express and stumbled on this code (after conversion the Express VI into a Subvi and then by opening the front panel):

What is happening with the conversion to decimal fixed values that look like they must be integers (in the red boxes)? Why these conversions would be useful?

Here is the micro-optimisations to help the synthesis tools to minimize the number of bits used in these code paths. The iteration Terminal is 32 bits wide and also involves a logic to do in the face of what is happening when the maximum value is reached. We have seen some benefits from the reduction of this path to the minimum width required both that which is written. I think it is probably still the case since the compiler usually does not know how many times a given line will run with a dynamic stop like this condition.

The optimization of the meter width is similar, taking advantage of the fact that we know that we have limited storage space to use circular buffers power-of-2 size. Using the exact number of bits of the address allows us to implement a counter of reversal with no additional logic. otherwise, we would need to check the value, and add a mux (Select) to reset the counter when it reaches the maximum value.

Synthesis tools usually do a good job of optimizing the unused bits, but here are two cases where we can help them by being more explicit about what we really need.

Tags: NI Software

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