FPGA Compilation fails because of the mistake of Xilinx

My FPGA compiles and I cannot understand why. There is nothing crazy in my FPGA VI of really, it seems strange to have this type of problem. I can't reach the code because its owner, but it's pretty simple because it reads all channels from a single module and records them in a data FIFO. I have compiled successfully any FPGA code on this computer, so I should definitely have everything needed to compile.

My system consists of one NOR cRIO 9030 with a single module 9220. Below is the Compilation of summaries.

---

LabVIEW FPGA: Compilation failed due to an error of Xilinx.

Details:
ERROR: [Synth 8-1031] knidmahighspeedsinkbase is not declared [/ opt/apps/NIFPGA/jobs/mC683d5_WCf98Qm/PkgShimSwitchedLinkDmaPortIfc.vhd:295]
ERROR: [Synth 8-1031] knidmahighspeedsinksize is not declared [/ opt/apps/NIFPGA/jobs/mC683d5_WCf98Qm/PkgShimSwitchedLinkDmaPortIfc.vhd:296]
ERROR: [Synth 8-1031] knidmahighspeedsinkbase is not declared [/ opt/apps/NIFPGA/jobs/mC683d5_WCf98Qm/PkgShimSwitchedLinkDmaPortIfc.vhd:301]
ERROR: [Synth 8-1031] knidmahighspeedsinkbase is not declared [/ opt/apps/NIFPGA/jobs/mC683d5_WCf98Qm/PkgShimSwitchedLinkDmaPortIfc.vhd:302]
INFO: [Synth 8-2810] pkgshimswitchedlinkdmaportifc unit ignored due to previous errors [/ opt/apps/NIFPGA/jobs/mC683d5_WCf98Qm/PkgShimSwitchedLinkDmaPortIfc.vhd:68]
---------------------------------------------------------------------------------
Development of finished RTL: time (s): UC = 00:00:07. delay = 00:00:31. Memory (MB): peak = 798.605; gain = 204.203
---------------------------------------------------------------------------------
ERROR: [Common 17-39] 'source' is not due to previous errors.
INFO: [Common 17-83] release license: synthesis
3 info, 0 Warnings, 0 critical warnings and 4 errors.
synth_design failed
: ERROR: [Common 17-39] 'source' is not due to previous errors.

When running
«source - notrace.» /. Xil/Vivado-6035-ip-10-60-203-176/realtime/toplevel_gen.tcl ".
called inside
«synth_design-top "toplevel_gen" - part "xc7k70tfbg676-1"-"full" flatten_hierarchy "»»
(file "/ opt/apps/NIFPGA/jobs/mC683d5_WCf98Qm/synthesize.tcl" line 21)
called inside
"source" / opt/apps/NIFPGA/jobs/mC683d5_WCf98Qm/synthesize.tcl "" "
exit #.
INFO: [Common 17-206] exit Vivado at Tue Mar 24 23:58:54 2015...

Compile time
---------------------------
Introduction date: 24/03/2015-16:46
Date recovered results: 24/03/2015-17:00
Waiting time in the queue: 00:24
Compilation of time: 13:22
-Generate a Xilinx IP: 00:00
-Summarize - Vivado: 01:27

Compilation has restarted on
24/03/2015-16:57

---

Any help would be much appreciated!

Thank you

James.Morris wrote:

Okay, so it seems that I get the error with a project from scratch and an FPGA with a single command and an indicator.

I download the latest FPGA 2014 SP1 installation and I hope that will solve my problem.

Well I'll mend, which fixed the problem! Somewhere along the line, my install FPGA must be corrupted.

Thanks for the help, guys.

Tags: NI Software

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