FPGA/FPGA adapter creates 250 mV voltage offset

I use a high-7971R FPGA in a chassis SMU-1073 with the adaptation Module 5782 (DC coupling) and 2016,08 device drivers. When I turn on the chassis and my computer, nothing strange happens. When I try to run something on the FPGA, however, things get weird. Each piece of code works exactly as it should, but as soon as that 'open FPGA reference' finishes running the adapter begins to produce a voltage mV to 0 to + 250 Ai and AI 1. It doesn't go to AO 0 or 1 AO. This shift of power disappears temporarily as long as 'Reference FPGA open' or "Close FPGA reference" are running, but the only way to get rid of the tension of offset entirely is to restart the chassis. Can someone explain to me why this is happening and how to fix it? The FPGA code, I am running can handle a small shift, but this shift seems to be to saturate the signal.

To see the shift: branch I HAVE 0 and AI 1 directly in a 1 M complete oscilloscope.

It is planned. CDA on this FAM (and more high-end a/d converters) have a range of sampling which is not centered around zero. The front end of the compenstates of the FAM for this by applying an offset from the signal which would appear to the user that the range of the ADC is centered around zero. What is different between this FAMILY and other instruments, is that it is not an additional circuit preventing that this lag observed a user of height of the output of the analog input.

You see the shift happen to reference open FPGA is because that's when power to the GPA is activated. The shift should not have an effect on reading which provides the analog input. Just make sure you have impedance corresponding to the source of the signal at the analogue input and you should be good.

Tags: NI Hardware

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