How to implement point filters fixed for FPGA

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  Filipe

  280584 wrote:
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  Hello

  Use this api
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  Kind regards
  pp

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• tables of fixed size in FPGA compilation error - how to implement a waveform control in an FPGA?

  Hello

  After being stuck for two days, please let me briefly describe my project and the problem:

  I want to use the cRIO FPGA for iterative control of waveforms. I want to capture a full period of the waveform, subtracting a reference waveform period and apply control algorithms on this. Subsequently the new period of correction must be sent again for the output module OR. If it does not work, the captured waveform will look like the one reference after several iterations.

  I am planing to create an array of size fixed for the capture and the reference waveform (each around 2,000 items for a given period). I use so 2 paintings of each elements of 2000. I use the function 'replace the subset of table' to update each element captured in the loop sampling and a feedback for each table node to keep in memory (I also tried shift registers, but then the berries do not have a fixed size any more and I can't start the compilation process).

  If I try to compile the FPGA vi, I get the following error:

  Details:
  ERRORortability:3 - Xilinx this application runs out of memory or met a memory conflict.  Use of current memory is 4167696 KB.  You can try to increase physical or virtual memory of your system.  If you are using a Win32 system, you can increase your application from 2 GB to 3 GB memory using the 3 G switch in your boot.ini file. For more information, please visit Xilinx answer Record #14932. For technical support on this issue, you can open a WebCase with this project attached to http://www.xilinx.com/support.
  "Synthesize - XST" process failed

  Before I added berries to my code I could compile the FPGA without problems. So, it seems that the tables are too big for the FPGA. :-(

  Therefore, I would like to ask if there is perhaps a better method to implement my problem in LabVIEW FPGA? How could avoid the tables to save my waveforms on a period?

  Thanks a lot for your help in advance.

  Best regards

  Andreas

  Unfortunately, the LabVIEW FPGA compiler cannot deduct stores shipped from berries (yet). When you create these two large paintings, you are creating essentially several registers very, very large. Just by looking at your picture, I guess that there are at least 4 copies of each of the tables.

  You want to use LabVIEW FPGA memories instead. You can create memories outside the loop and then read/write them where you are currently referencing the berries. The only change that you really need to do is to break down your treatment in scalar operations. I have attached a simplified version of your plan, I hope it helps. Let us know if you have any other questions.

  

• How to implement Canopen on FPGA to run the engine using NOR-9881?

  Dear,

  Your support will be highly appreciated,

  There is only one available for NOR-9881 example.
   
  Please note that the following materials were properly connected:
  cRIO-9024, cRIO-9113, OR-9881 and motor Nanotec (SMCI36 against L2818L0604-T5X5), the following
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  1 - example Nanotec: dependent VISA controls for data transfer
   
  http://us.Nanotec.com/support/application-notes/LabVIEW-example/
   
  2 - reference example CANopen for series C OR - 9853 Module CAN:
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  http://zone.NI.com/DevZone/CDA/EPD/p/ID/6093
   
  3 - from finder labView example: search for 9881 then choose
  NOR - CANopen_cRIO.lvproj, which depended on SDO orders for transfer orders
   
  The attached picture shows that NEITHER-9881 can be seen, after compilation and
  loading the bitfile FPGA.
   
  Please, please advice me:
  1. how to start?
  2. how to create variables of entry for NI9881?
  3. how to implement CANopen mode FPGA? where there is no CANopen palette.

  Thanks in advance and

  Hello!

  From my understanding, the 9881 can be treated from the FPGA, but only from the application of the RT. I think that the point 3 of your post examples of the use of the module fine.

  Kind regards

  Georg

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