Initialization of the DRAM in FPGA

To test my FPGA (FlexRIO 7966), I tried to test the error trapping.  Generally, the error would be caused by an overflow in the FIFO of DMA process (EX: host VI is not reading fast enough causing the FPGA DMA fifo fill then causing my DRAM FIFOs to fill).  When this happens, simply reload the bitfile does not seem to clear the condition.  The memory is still in the complete state.  Even restart the controller does not seem to clear the error.  Electric bike does not work, but it's no possible to retrieve errors.

It is impossible to probe whose memory is in trouble, so I ask:

1. when the bitfile is loaded and running, the DMA FIFO is reset?  What of the DRAM (configured as FIFO)?  Or General FPGA FIFO memory (Blockram, registers, etc.)?

2. it would be of no use to manually clear the DRAM during the initialization of the FPGA (EX: switch from data_available to read in a SCTL initialization until data_available is set to false and ignore the actual data)?

File guides and aid users are very light on works the initialization of FPGA.

Thank you

xl600


Tags: NI Software

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