Integration of IP node evil in LabVIEW FPGA

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• LabVIEW FPGA: Integration node clock wrong

  Hello

  I'm having some difficulties to understand how the clock is part of the node IP for LabVIEW FPGA and was hoping to get some advice.

  What I try to do is to set up a digital logic circuit with a MUX feeding a parallel 8-bit shift register. I created the schema for this Xilinx ISE 12.4, put in place and can't seem to import the HDL code into an intellectual property node. When I run the VI, I am able to choose between the two entries for the MUX, load the output in the shift register, clearly the shift register and activate the CE.

  My problem is that when I switch to the entrance of THIS, he should start 1 sec shift (Boolean true, SCR, High, what-have-you) in the registry once each clock period. Unfortunately, it instantly makes all 8 bits 1 s. I suspect it's a question of clock and here are some of the things I've tried:

  -Specify the input clock while going through the process of configuring IP nodes.

  -Adding an FPGA clock Constant as the timed loop.

  -Remove the timed loop and just specifying the clock input (I'm not able to run the VI that I get an error that calls for a timed loop)

  -Do not specify the clock to enter the Configuration of the IP node and wiring of the FPGA clock Constant to the clock input (I can't because the entry is generated as a Boolean).

  -Remove an earlier version of the EC who had two entries up to a door and at ISE.

  -Specify the CE in the process Configuration of the IP nodes.

  -Not specify this in the process of setting up nodes IP and wiring it sperately.

  -Various reconfigurations of the same thing that I don't remember.

  I think I'm doing something wrong with the clock, and that's the problem I have. Previously, when I asked questions to the Board of Directors on the importation of ISE code in LabVIEW FPGA, a clock signal is not necessary and they advised me to just use a timed loop. Now, I need to use it but am unable to find an explanation online, as it is a node of intellectual property.

  Any advice would be greatly appreciated, I'm working on a project that will require an understanding how to operate clocks the crux of intellectual property.

  Thanks in advance,

  Yusif Nurizade

  P.S. I have attached my schematic ISE and the LabVIEW project with one of the incarnations of the VI. The site allow me to add as an attachment .vhd file, but if it would help I could just paste the body of the code VDHL so just let me know.

  Hello Françoise,.

  I spoke to the engineer OR this topic and it seems that it was sufficient to verify that your code works, by putting a wait function of 500 ms on the while loop to check that the registers responsible and clear. I'm glad that it worked very well!

• Integration of IP node: VHDL + LAVIEW FPGA

  Dear members

  can I use a library set by the user or a parcel inside the IP integration node?

  for example library that contain a function for fixed operations in comma?

  As

  Library IEEE;
  Use IEEE. STD_LOGIC_1164.ALL;

  Use mustafa... pkg

  Unfortunately, there is no way to directly access a block of memory of LabVIEW FPGA and an IPIN node. You will need to file a read/write memory next to your IPIN node node and manage lines of coordinates and data of your IPIN node as ports.

• Move from LabVIEW FPGA block of ram address to node CLIP?

  Hello

  I need to pass an index memory RAM of LabVIEW FPGA block to a CLIP node to the node CLIP to have access to the data in the BRAM.  The node of the ELEMENT contains an IP address that we developed and the IP address is the use of Xilinx BRAM driver to access data.  I guess that we need to move the physical address of the BRAM to the ELEMENT node.

  Is this possible? If so, how? If this is not the case, what would be an alternative?

  Thank you

  Michel

  If I understand you correctly, Yes, you should be able to use the memory block of the Xilinx pallet Builder in LabVIEW FPGA and in the loop of the single Cycle, connect the ports of this block signals CLIP exposed by the IP of your colleague. You may need to tweak/adapt some of the signals slightly to the LabVIEW data flow.

• LabVIEW FPGA CLIP node compilation error

  Hello NO,.

  I work on an application for my Single-Board RIO (sbRIO-9601) and faced with a compile error when I try to compile my FPGA personality via the ELEMENT node.  I have two .vhd files that I declare in my .xml file and all at this point works great.  I add the IP-level component to my project and then drag it to the VI I created under my FPGA.

  Within the FPGA personality, I essentially have to add some constants on the indicators and entries CLIP to my CLIP out and attempt to save/compile.  With this simple configuration, I met a compilation error (ERROR: MapLib:820 - symbol LUT4... see report filling for details on which signals were cut).  If I go back to my VI and delete indicators on the output (making the output pin of the CLIP connected to nothing), compiles fine.

  I've included screenshots, VHDL and LV project files.  What could be causing an indicator of the output of my VI to force compilation errors?

  Otherwise that it is attached to the output ELEMENT, a successful compilation...

  

  After that the output indicator comes with CLIP, compilation to fail...

  

  NEITHER sbRIO-9601
  LabVIEW 8.6.0
  LabVIEW FPGA
  Windows XP (32-bit, English)
  No conflicting background process (not Google desktop, etc.).

  Usually a "trimming" error gives to think that there are a few missing IP.  Often, a CLIP source file is missing or the path specified in the XML file is incorrect.

  In your case I believe that there is an error in the XML declaration:

  
    1.0
    RandomNumberGenerator
   
      urng_n11213_w36dp_t4_p89.vhd
      fifo2.vhd
   

  This indicates LV FPGA to expect a higher level entity called "RandomNumberGenerator" defined in one of two VHDL files.  However, I couldn't see this entity in one of two files.  If urng_n11213_w36dp_t4_p89 is the top-level entity, edit the XML to instead set the HDLName tag as follows:

  urng_n11213_w36dp_t4_p89

  Also - in your XML, you set the 'oBits' music VIDEO for output as a U32, however the VHDL port is defined as a vector of bits 89:

  oBits: out std_logic_vector (89-1 downto 0)

  These definitions must match and the maximum size of the vector CLIP IO is 32, so you have to break your oBits in three exits U32 output.  I have added the ports and changed your logic of assignment as follows:

  oBits1(31 downto 0)<= srcs(31="" downto="">
  oBits2(31 downto 0)<= srcs(63="" downto="">
  oBits3(31 downto 0)<= "0000000"="" &="" srcs(88="" downto="">

  Both of these changes resulted in a successful compilation.

  Note: The only compiler errors when you add the flag because otherwise your CUTTING code is optimized design.  If the IP is instantiated in a design, but nothing is connected to its output, it consumes all logic?  Most of the time the FPGA compiler is smart enough to get it out.

• Question for LabVIEW FPGA DRAM

  Hi all

  How can I correctly address the 128 - bit DRAM memory?  I have the Bank DRAM 0 set as a memory of 128 bits, set up in my design as a CLIP.  I realize it's a wide RAM on 32-bit.  I had a National Instruments AE do the original design I've been adding to.  He said that the addresses needed to incrementing by four with each entry.  Example: if I had to write in consecutive addresses, I would write to the address: 0, 3, 7, 11, 15 etc, and I would like to send 128 bits to each address.  My address is calculated as: (number of pixels in a line of video + line * (number of pixels per line) for a picture of the video).  So I take my calculated address and add 4.

  However, I checked an example in the finder example: example of integrity hardware flexRIO/IO/external memory/memory.  In this example, 128-bit data is sent to the memory and the address is incremented by 1 (instead of 4) each cycle clock as valid data.

  Who is this?  Section of the help for this function is ambiguous.

  Sets the address in external memory for reading or writing. The physical data bus for external memory is 32 bits wide (4 bytes). Each unique address value represents 4 bytes of data. Therefore, the total number of unique addresses in external memory is equal to (Memory Size in bytes)/4.  
  
  Note  The memory interface exposed to LabVIEW FPGA is 128 bits wide. As a result, each memory write or read operation accesses four different address locations in memory. The memory controller latches this signal value only when you issue a new memory write command by asserting the Command_Write_Enable signal.
  

  I'm confused by the 2nd paragraph "every Scripture memory or read operation four access address locations of memory."  Does that mean I increment the address by 1 to get 128 consecutive bits 'locations' (Yes, I know, that's 4 words of 32 bits in memory), or do I increment the address by 4, in the order of words of 32 bits 4 by 128-bit single transfer?

  Thanks for your help.

  -J

  Hello J,

  I want to clarify my previous post.  There are two ways to access memory DRAM, CLIP (that you have described is what you do) and using the memory node.  As noted before, the DRAM is 128 bits wide.  When you write to the CLIP you basically write pieces that is the width of the databus (in this case 32-bit).  Therefore, when you write a total of 128-bit DRAM, you place 32 bits in each address.  The address being the width of the databus, then you write with a writing & the address 0, 1, 2, 3.  Then the next write will be 4, 5, 6, & 7 and then address 8, 9, 10, & 11 and so on.  In this case, you must increment your address by 4 whenever you write.  Note that you start at 0, then 4, then 8, etc 12.  In your previous post, you were out of a figure.

  There is also another way to write in the DRAM memory, and it is through the node of memory, which is what is used in the example that you are pointing out.  Here, LabVIEW takes on some of the thought, and instead of being the width of the databus address, they are the width of the entire segment of 128 bits.  So when you write to DRAM here, you only increment 1 whenever address because they refer to any segment of memory.  This contrast with the CLIP, address 0 of the memory node interface match the addresses 0, 1, 2, 3 in CLIP mode & and address 1 of the memory node would correspond to 4, 5, 6, 7 in CLIP mode addresses &.  If you do not write an integer of 128 bits for the memory node, then the remaining addresses in the data block are filled with "junk" so that the address remains constant.

  As I mentioned previously, it is the most effective writing in chucks of 128 bits so that you don't waste all of the DRAM.  I hope you find this explanation clearer.

  Brandon Treece

  Technical sales engineer

  National Instruments

• LabVIEW FPGA SPI accident - SPI OR IP address for example - R series OR

  Hello

  I am trying to run the series R - sample project NI SPI FPGA Simulation.lvproj that comes with the SPI IP OR on a real FlexRIO FPGA SMU-7976R target with an attached digital adaptation NI 6581 B Module. The example is for a PCIe-7841R but I wore during my target FPGA, follow these steps and made additional changes to try to make it work with my set-up. I learned that FlexRIO FAMs CLIPs do not work with nodes in office had so I know I can't simulate the project originally planned so I will try to use FPGA to e/s node host side (open FPGA vi reference) to implement the actual hardware.

  My first question concerns my configuration of the adapter module e/s and selection. I added the IO Module (NI 6581 B: NI 6581 B channel) for my project and selected the channels as shown in the table below. I have a real physical hardware connection as described below using two NI SHC68-C68-D4 cables and a break-out Board.

  

  I changed the names as well:

  

  I selected these DIO channels because I wanted the DDCA connector to be the master and the DDCB connector to be the slave. In addition, in this CLIP every eight channels of i/o has a write enable signal. I have not used the Port configuration because I needed 4 available DIO channels and I saw DIO0-3. Is my logic of selection of channel vs correct Port here?

  Following the same strategy that examples FlexRIO/NI6581B, I changed the FPGA.vi to include initialization outside of timed loops:

  

  And in the Host.vi I have a node reference FPGA and wired loops of feedback accordingly:

  

  When I compile the FPGA and try to run Host.vi LabVIEW inevitably crashes with Crash Reporter below and must restart:

  

  Does anyone know what I'm doing wrong here? My guess is that it has something to do with the CLIP/IOModule. Any help is appreciated.

  Thank you

  Scott

  Hi Scott,.

  I suspect that the problem might be related to the fact that your node open FPGA VI reference is in the while loop and trying to open a new FPGA reference at each iteration.
  If you move outside of the while loop, it does not solve the crash?

  On channel vs port question, your logic seems reasonable to me, but I recommend to try it since this feature could depend on device.

• Internal software error of LabVIEW FPGA Module - 61499

  I get the error next (in a pop-up window) in the phase of sompilation for the FPGA target with a vhdl IP. This error continues to occur even after restart LabVIEW and the PC. Someone at - it solved is this kind of problem before without having to re - install the software?

  Here is the error information:

  Error-61499 occurred at niFpgaXml_GetValue_String.vi<><><><>

  Possible reasons:

  LabVIEW FPGA: An internal software error in the LabVIEW FPGA Module has occurred. Please contact National Instruments technical support on ni.com/support.

  Additional information: lack the tag required XML (/ CompileServerList)

  As a first step, I can compile the vhdl IP node successfully. However, once when I'm running a VI with the FPGA, the bureau stop working. After that I restarted by force, it cannot perform the build of a vhdl IP node. Even without connecing to the jury of LabView, he pointed out errors before the end of the sompilation.

  Interestingly, the screw which also includes nodes IP vhdl that I properly compiled before, I can still run the VI to the Commission and it works correctly.

  Thank you

  Looks like your ActiveJobsList somehow has been corrupted. I saw occur when computers are hard stop or blue screen during compilation. I don't have that LabVIEW 2014 installed on my machine, so your path will be a little different, and the file extension will be a .txt or .xml instead of .json, but try this:

  Move the file "C:\Program Files (x 86) \National Instruments\LabVIEW 2014\vi.lib\rvi\CDR\niFpgaActiveJobList.json" (or your equivalent) out of the above directory (back it upward and delete essentially) and restart LabVIEW. Must regenerate the file and resolve the problem.

• How to measure the frequency of sampling (s/s) in LabView FPGA?

  Hello

  I am trying to find a way to measure the sampling frequency (s/s) during which I read from analog input in LabVIEW FPGA. I know that the sampling frequency is specified in the data sheet of the module HAVE, but I want to measure in LabVIEW.

  Any suggestions?

  A screenshot of the example code would be greatly appreciated

  Hey phg,.

  If you have some time loopand in this loop, you export a sample by iteration of loop via an I/O node. You can't out two samples on the same I/O node within an iteration, it's always one!

  So if your loop takes 1 second to run you have a sampling rate of 1 Hz output. The same goes for sampling of entry. How long your loop takes to run can be calculated as explained above.

  Samplerate [s / s] = 1 / [s] while loop

• LabVIEW FPGA: Problem compiling look-up Table

  Current versions of software:

  LabVIEW 2014 SP1

  LabVIEW FPGA 2014

  Xilinx Vivado

  I'm having a huge problem in trying to compile my LabVIEW FPGA code.

  Some recall of the code:

  It's all in a SCTL.

  I am streaming in a FIFO DMA and comparing it with the values previously stored in the shift registers (which are initialized to 0 at the start of the loop) in the SCTL.

  The results of the comparison are then piled into a U16 and loaded into a lookup table (I use the LUT - 1 d), and I'm so help this LUT to decide what value will be charged to travel to record for the next iteration of the loop, which, in any case, would be either the current values of the flow, or the post previous registry value.

  (It's a triage loop)

  I am able to run very well in simulation mode code, but when I try to compile, I get this error:

  "The selected object has a built-in shift register that makes the output on a particular loop iteration correspond to the entries in the previous iteration."

  Connect the outputs of the object directly to a minimum number of nodes of Feedback or uninitialized shift registers. You cannot connect the outputs to another object.

  See using LabVIEW for more information on the objects with registers embedded offset. »

  Someone at - it ideas why this happens, and what might be the possible solutions?

  I'm tempted to break it down into separate loops, but I prefer not to because it is now a loop (and working in my simulation).

  I found my problem.

  Any time that a LUT is in a chain shift register, it cannot:

  1. be part of a string of shift register that has a variable initialized

  2. follow-up to no decisive structure, like a box structure.

  I just moved the position of LUT and it works.

• Spartan - 3 driver and Labview FPGA 2009

  Hello

  Do we need a new Spartan-3E driver to work with Labview FPGA 2009? And, if so, is it provided by National Instruments?

  Thank you

  Walid F. van

  Hello everyone

  The driver for the Spartan 3rd WHAT XUP Starter Kit are now on the site OR here:

  http://digital.NI.com/express.nsf/bycode/Spartan3E?OpenDocument&lang=en&node=seminar_US

  Just click on the link to get driver.

  Kind regards

  John Harvey

• Configuration of the inputs/outputs of NI9401 in labview FPGA

  Hello

  I am very new to Labview FPGA. In fact, I'm implementing the very first example introduced by OR for learning Labview FPGA. I need to connect an entry of a NI9401 on one exit from the other.

  However, when I drag and drop the input/output units, the two act as inputs:

  

  I also changed the propties one of the NI9401 to act as output. But the problem persists.

  

  It is the example that I am building.

  I'd appreciate any suggestions.

  https://www.YouTube.com/watch?v=mv112V-P030&index=1&list=PLbCk9hRe-ziECXQjE--fN29C_kcx7CHnA

  Right-click on the output node, and then select "change to write."

• Model a block synchronous dual-port RAM with LabVIEW FPGA

  This question caught my attention recently.

  I am trying to model a particular design element called "RAMB4_S8_S8" with the LabVIEW FPGA module. This element is a block synchronous dual-port RAM allowing simultaneous access to two ports independently from each other. That being said, a port can perform read/write operation to this RAM while at the same time, the other port might be able to do the same thing. There are two opportunities of possible port conflict, however. The first is when both ports are trying to write to the same memory cell. The other scenario is when a port writes in a cell memory while at the same time the other port reads from it. Other than that, everything should be a legitimate operation.

  In order to reproduce this I select memory block that is integrated into my FPGA target. An interface is configured to be the playback mode, and the other is set to write fashion. For the option of arbitration, I let the two interfaces to be "arbitrate if several applicants only. Then I got a compiler error when I tried to run my FPGA code for this model in a SCTL. The error message is something like "several objects to request access to a resource through a resource configured with option interface" arbitrate if several applicants only ", which is supported only in the single-cycle Timed loop if there is only a single applicant by interface.

  This error goes away if I replace the SCTL with a simple while loop, but not what I would like to implement. So I wonder if there is a better solution to this problem, or is it just the limitation of the LabVIEW FPGA module.

  Thank you.

  Yes, you can use a form of conduct to perform the operations you want in the generations clock cycles, but all the code is inside a single SCTL. Basically, read the first address and storing in a register in a single cycle and then read the second address in the second clock cycle. This would allow you to two readings of valid memory every clock cycle 2. I have included a crude extract to illustrate the concept. The case selectors are identical with address A being connected to the memory in the true case, B in the case of fake address. Your biggest model memory dual port will be intact, but it will operate at 1/2 rate.

  Take a look at the white paper that provides more details on the construction of memory:

  Data on a target FPGAS (FPGA Module)

  The ball on the memory block indicates that memory block double port cannot be applied in a configuration of reading, which is a double ROM. access read/write port must be imitated with custom code.

• HELP - FPGA SPARTAN 3E-100 CP132 WORKS WITH LABVIEW FPGA?

  HI EVERYONE, GET ON IM TRYING TO USE MY FPGA WITH LABVIEW, BUT I DO KNOW THAT IF ITS COMPATIBLE, I INSTALLED THE DRIVERS, MODULE FPGA AND LABVIEW 2012, IM USING WINDOWS 7 32 BIT, AND AFTER I COMPILED ITS SAYS:

  LabVIEW FPGA called another software component, and the component returned the following error:

  Error code:-310601

  NOR-COBS: Impossible to detect the communication cable.
  Check the communication cable is plugged into your computer and your target. Also, verify that the proper drivers are installed.

  Thank you.

  =)

  Hi dvaldez2.

  LabVIEW FPGA offers no support for any material to third parties, other than the 3rd Spartan XUP Starter Kit. These are probably the drivers you downloaded.

  http://digital.NI.com/express.nsf/bycode/Spartan3E?OpenDocument&lang=en&node=seminar_US

  However, this driver supports only the Starter Kit Board itself (http://www.digilentinc.com/Products/Detail.cfm?NavPath=2, 400, 790 & Prod = S3EBOARD). You may not use the driver with any other Xilinx FPGAS.

  I hope this helps.

• How to import codes Verilog in LabVIEW FPGA?

  I tried to import the Verilog code by instantiating followed education in http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3.

  but I can still see some errors when compiling the file VI.

  Test file simple Verilog is as follows:

  ==============================

  module andtwobits (xx, yy and zz);

  input xx, yy;
  output reg zz;

  always start @(xx,yy)
  ZZ<= xx="" &="">
  end
  endmodule

  ==============================

  and after you follow the above link, we have created the instantiation as file

  ==============================================

  Library ieee;
  use ieee.std_logic_1164.all;

  mainVHDL of the entity is
  port)
  xxin: in std_logic_vector;
  yyin: in std_logic_vector;
  zzout: out std_logic_vector
  );
  end mainVHDL;

  architecture mainVHDL1 of mainVHDL is

  COMPONENT andtwobits PORT)
  ZZ: out std_logic_vector;
  XX: in std_logic_vector;
  YY: in std_logic_vector);
  END COMPONENT;

  Start

  ALU: andtwobits port map)
  ZZ-online zzout,
  XX-online xxin,
  YY-online yyin);

  end mainVHDL1;

  ==============================================

  Sometimes, we observe the following error when we put the flag on the output port.

  ERROR: ConstraintSystem:58 - constraint

  TNM_ChinchIrq_IpIrq_ms; > [Puma20Top.ucf (890)]: INST
  "* ChinchLvFpgaIrq * bIpIrq_ms *" does not correspond to design objects.
  ERROR: ConstraintSystem:58 - constraint
  TNM_ChinchIrq_IpIrq; > [Puma20Top.ucf (891)]: INST ' * ChinchLvFpgaIrq * bIpIrq. "
  does not match design objects.

  and Interestingly, if we remove the indicator from the port of exit, he sucessfully compile on the LabVIEW FPGA.

  Could you take a look at and please help me import Verilog to LabVIEW FPGA?

  I followed the basic steps of the instantiation on the link above, but still it will not work.

  Please find the attachment for all files.

  -andtwobits.v: original file from Verilog

  -andtwobits.ngc: file UCS

  -andtwobits.vhd: VHD file after translating a simulation model

  -mainVHDL.vhd: master of the instantiation

  Since there is no sample file for Verilog (VHDL file, there but not for Verilog), it's a little difficult to do simple execution on LabVIEW FPGA, even for examples.

  Thank you very much for your support, and I'm looking forward to seeing all your help/answer as soon as possible.

  Records,

  The best instructions we have for integration Verilog IP in LabVIEW FPGA can be found here: using the Verilog Modules in a component-level design. My suspicion is that you did not uncheck the option 'add the IO buffers' in the Xilinx ISE-specific Options parameter when running XST (see page 8 of the .pdf)