Jitter of RT! Can multiple readings to a variable / cluster cause a deadlock condition?

Howdy do.

While gradually develop and test an application on a crio9068 (RT linux) I started to see 'finished later?' in my main timed loop indicator flicker. Start pulling my hair out trying to figure out how to prevent this. I did a 'max hold' vi and can see the longest execution time for each image.

The application runs fine at about 75% of CPU with the Panel open load, and the majority of the iterations run at the time. Sometimes I'll have a 'pic' at run time, all four managers in the timed loop take significantly longer than normal to run and the indicator 'late' says.

A few questions I've had accumulate while chasing this:

-If I use local varables to pass data between the loops, but only write to the variable in one place, can I still cause a condition of blocking/jitter by competing readings of this memory space?

-If I use a node FPGA read/write to pass data between the FPGA and the timed loop, I should expect this causes a problem? I selectively disabled a lot of my code, and it seems that is where some of the delay occurs. What me stem, it's that these parts of the code have not changed in the recent development and the thing never used to run to the end.

-On the theme of the node FPGA read/write, I assumed before that I should not write to the same FPGA FP element in different subvis. However, the code is set up so that there are several parallel calls to the read/write node, just with different selected items. Is that BAD?

-Similarly, if I ungroup and read the same item in a cluster in a "parallel" mode control, can this cause a deadlock situation, or is it the same as unbundling and wiring away in several places?

-I am thanks to the recently renamed "software calibration and management toolkit NI (SCM)," formerly Drivven CalView, to manage the communication between the RT and a windows host. He is also careful fault management stuff. Anyone else using it, and is it possible that I am getting jitter by having too many calpoints in my deterministic loop?

No indication on any of the above would be greatly appreciated. If I don't make sense on any of the above points I do excerpts from example to describe.

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Hi Matt,

What about under the name of multithreading - the same thread can run on multiple cores, but everything in a timed loop will always hold in a single thread.  For reference (see 'Set the execution order for screws of real-time synchronization'):

LabVIEW Help: Synchronization of deterministic Applications (real time Module)

http://zone.NI.com/reference/en-XX/help/370622L-01/lvrtconcepts/timing_control_loops/

To cache the runtime data, I didn't have a specific method for mind, rather I generally try to catch at least one instance of the hiccups by capturing variables of interest in the shift registers or a FGV, just to see if there is any kind of difference.  This may not be useful in your case, as I suspect it's interactive execution, what causes the problem.

Regarding the interactive performance and determinism, there is really no way of knowing what will happen, but it will often cause the kind of behavior that you see now. Because you are more or less continuous between the target and the host data, everything hangs in the network or on the computer host can set the RT system, especially if you read or write data on the front panel. Given that all of your curls are delayed at the same time, it seems the most likely scenario, unless you have a VI reentrant or similar shared between all the loops - I have seen that a few times with managers error or stop sharing.  Given that these spots are quite often (it resembles something like 1/100 iterations, I would recommend put in some shared variable RT FIFO benchmarking and the deployment of the application as a stand-alone RTEXE.)  It should be fairly easy at that time see if instability persists.

Best regards

Tags: NI Software

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