LabVIEW FPGA CLIP node compilation error

Hello NO,.

I work on an application for my Single-Board RIO (sbRIO-9601) and faced with a compile error when I try to compile my FPGA personality via the ELEMENT node.  I have two .vhd files that I declare in my .xml file and all at this point works great.  I add the IP-level component to my project and then drag it to the VI I created under my FPGA.

Within the FPGA personality, I essentially have to add some constants on the indicators and entries CLIP to my CLIP out and attempt to save/compile.  With this simple configuration, I met a compilation error (ERROR: MapLib:820 - symbol LUT4... see report filling for details on which signals were cut).  If I go back to my VI and delete indicators on the output (making the output pin of the CLIP connected to nothing), compiles fine.

I've included screenshots, VHDL and LV project files.  What could be causing an indicator of the output of my VI to force compilation errors?

Otherwise that it is attached to the output ELEMENT, a successful compilation...

After that the output indicator comes with CLIP, compilation to fail...

LabVIEW 8.6.0
Windows XP (32-bit, English)
No conflicting background process (not Google desktop, etc.).

Usually a "trimming" error gives to think that there are a few missing IP.  Often, a CLIP source file is missing or the path specified in the XML file is incorrect.

In your case I believe that there is an error in the XML declaration:


This indicates LV FPGA to expect a higher level entity called "RandomNumberGenerator" defined in one of two VHDL files.  However, I couldn't see this entity in one of two files.  If urng_n11213_w36dp_t4_p89 is the top-level entity, edit the XML to instead set the HDLName tag as follows:


Also - in your XML, you set the 'oBits' music VIDEO for output as a U32, however the VHDL port is defined as a vector of bits 89:

oBits: out std_logic_vector (89-1 downto 0)

These definitions must match and the maximum size of the vector CLIP IO is 32, so you have to break your oBits in three exits U32 output.  I have added the ports and changed your logic of assignment as follows:

oBits1(31 downto 0)<= srcs(31="" downto="">
oBits2(31 downto 0)<= srcs(63="" downto="">
oBits3(31 downto 0)<= "0000000"="" &="" srcs(88="" downto="">

Both of these changes resulted in a successful compilation.

Note: The only compiler errors when you add the flag because otherwise your CUTTING code is optimized design.  If the IP is instantiated in a design, but nothing is connected to its output, it consumes all logic?  Most of the time the FPGA compiler is smart enough to get it out.

Tags: NI Hardware

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