NEITHER 9234: sampling rate: cRIO, FPGA

For the NI 9234 module, before Panel block diagram of my my cRIO FPGA code is as below.

The sampling rate (speed) is selectable between certain values as shown below.

You have an idea how I can do the sample with a lower rate that is smaller than the option of character (1.652 ksps / s)?

Hi Cashany,

Take a look at this link. Page 16 describes the limitation that you run in. The main time base are divided essentially only toward down to some data because of the way the camera rates physically handles analog and digital filitering. So it's not really a way to divide the beyond that point.

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