noise in the Vref for pipeline ADC 14 bit

I work with a pipeline of 14 bit ADC clock of 10 MHz. The total of entry is 4 Vp - p bonus.

There seems to be a lot of noise in the VRef (about 50 mV swing noise) and tensions are given directly from feeding to the ADC.

What are the ways to reduce this noise?

Maybe not good advice. It is a pure analog circuit

... but what do you expect to answer if you do not give detailed information on the references used, ADC used, schematic and layout?

However, to seek application of technology notes linear www.linear.com (look for those of Jim Williams!)   and texas Instr. TI.com

Find a Council of analog circuits and post your question, some screenshots of scope, schema, and page layout, he...

Tags: NI Hardware

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