Open FPGA references change to no. target when compiled with executable in time real start
Hello again you useful forum fans! I have a problem that I hope someone can give me a hand with.
I have a project that has a Windows component and a component of the target in real time, that are running on a hypervisor type NI PXI-8110 system. Communication both sides between them using shared variables.
On the real-time side, I have four FPGA targets who are reading and writing various analog and discrete inputs and outputs. I several periods loops which opens a reference to one of the FPGA targets during the first call, then pass this reference in several subVIs that read and write to panels prior to the FPGA. The loops the FPGA reference thus made available and reuse it in the next iteration through the shift registers. Each FPGA target has only a single reference open to him. One of the loops is using the FPGA reference directly and does not pass it in any subVIs.
It all works very well in the development environment, I can read and control inputs and outputs FPGAS via the front panel of the application of the side Windows. It also works very well if I start the game real time in the development environment, and run the code of windows as a stand-alone executable file.
However, when I compile the code in real-time in an executable startup and deploy it to the target, it does not work. I enabled debugging on the executable, and when I connect to it via the operation-> debug executable in the menu, I see an arrow broken at execution. Further investigation shows that each of the four open screw reference FPGA is now empty, the text under them is "no target" and the thread for reference on their part to my first Subvi is broken. I need your help to understand how to operate as it does in the development environment.
I followed the instructions of these two knowledge base articles to compile and download the bitfiles FPGA on the FPGA target and execute on start or restart:
http://digital.NI.com/public.nsf/allkb/39795847AC67296D862575FB0046944F
http://digital.NI.com/public.nsf/allkb/BC513C2A0DC29C89862574BF0002B0B9?OpenDocument
Open FPGA reference screw are configured for the FPGA to build specifications that I created for each target in the LabVIEW FPGA project.
I called technical support, NO phone, and yet were able to determine this one out, so additional "brownie" points if you do! I would offer you the same no detailed screenshot that I have (I can't give more detailed code out because its owner, unfortunately), but apparently the forum doesn't like my image file, as I can't seem to load.
Please let me know if you have any ideas regarding what is happening! I appreciate it.
Jon,
I'm always up for the challenge. Have you tryied recompile the FPGA VI that accesses the RT VI? I also suggest to try and open the bitfile instead of the FPGA VI. You run in dynamic mode (this is not a suggestion, it's just a question)? There is no difference if you try to open the FPGA VI reference outside the while loop, then past the reference to use inside the while loop without shift registers, then close the reference to the FPGA VI outside the while loop?
Let me know if these suggestions makes no difference.
Tags: NI Software
Similar Questions
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I'm learning the FPGA. I have a few simple question.
1. I tried to use the open FPGA VI reference configuration. I selected the file bit on my PC, and I checked the run option VI FPGA. Why I select the bit file on my PC? The file bit is not supposed to be on my FPGA target?
2. once I open FPGA VI reference, I fed to an invoke node, but it won't. It is said that the sources and sinks have given different type, but he also says that they are both FPGA interface. I'm a bit confused.
Please see attached picture.
jyang72211 wrote:
1. I tried to use the open FPGA VI reference configuration. I selected the file bit on my PC, and I checked the run option VI FPGA. Why I select the bit file on my PC? The file bit is not supposed to be on my FPGA target?
Not quite sure what you're asking here. A FPGA target has no local storage. When you open the FPGA VI reference, LabVIEW support the bitfile on the FPGA. The VI that calls open FPGA VI reference is one that opens the bitfile, the bitfile must be local to this VI (in this case, on your PC).
jyang72211 wrote:
2. once I open FPGA VI reference, I fed to an invoke node, but it won't. It is said that the sources and sinks have given different type, but he also says that they are both FPGA interface. I'm a bit confused.
The FPGA reference on the Panel before you must match the configuration of the reference that you're passing to it. Right-click on the front panel control and configure the FPGA reference to point to the same bitfile you open. Better than that, bind the FPGA VI reference open to a Type definition and the place that the category definition on the Panel the Subvi front. Note that if you do this, it works at the back of what you would expect. Update of the baseline open FPGA VI changes the type definition; you never directly change the type definition.
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Open FPGA reference fails to run
Hello
I apologize if this is covered elsewhere; I found nothing relevant.
I have a fair size RT application that calls the vi FPGA reference open as the second point during initialization. The FPGA is compiled and worked fine before with a simpler application of the RT. When you run the program I probe the wires of the error as well as highlight the execution and the program is just stuck on that vi.
The vi is configured to point to the FPGA vi in the project. I tried pointing to the bitfile and the same behavior occurs.
The goal of the RT is a sbRIO 9631 with NOR-RIO installed 3.5.1 (without scan interface). I reinstalled it during my troubleshooting.
So with that, any suggestions? Otherwise, I can be on the phone with TOMORROW and will post whatever I learn.
In the same vein, it would be possible that the user interface is simply not updated because you use too many resources on the RT controller. Especially with probes and highlight the running, the transformation of the network might be causing a problem. In the measurement and Automation Explorer or distributed systems manager, you can view the sbRIO here memory/CPU usage:
http://digital.NI.com/public.nsf/allkb/8C7B655978C8ADFB86256AAE004AD261?OpenDocument
I would try also to Flash the sbRIO then reinstalling the 3.5.1 drivers on the device and try again. If you had a different version on the target as 3.5, it may have been a fix that resolves this.
Finally, try to have the FPGA vi to run when load/run when starting the crio by following these KBs:
http://decibel.NI.com/content/docs/doc-3076
http://digital.NI.com/public.nsf/allkb/BC513C2A0DC29C89862574BF0002B0B9?OpenDocument
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- If you use the indicator 8.x, you get a flat structure in the EXE. This is not your case, and I would not recommend it in any case.
- If the flag is set to false, LV basically takes all the screws that must go into the exe (static libraries dependencies and included screws) and places them in the EXE file using the same exact folder structure as code. This allows to undress and to build paths and having the code works the same way.
- Code that is located in the LV folder (such as the vi.lib code) is placed in a top-level called 1abv1ew folder, so it can be found.
- If you need to get the path of the folder, use the app dir VI.
- If you need to get a path to VI, use a static reference to the VI and a property node to get its path property. It works in dev and EXE.
- Virtual folders are not relevant (that they are not paths). AutoFill files are linked on the disk, so they do not reflect the path, but it's not really relevant. Jeff was simply pointing out that this may reflect the path and that he does not like them.
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