pipelining

Hi, just a theoretical question about pipelining in SCTL to the FPGA. On the help of sheet http://zone.ni.com/reference/en-XX/help/371599D-01/lvfpgaconcepts/fpga_pipelining/

I see that you can use shift registers which, after some time of latency, allows to have an output of each sub VI each loop cycle.

However in the diagram it shows the first output valid void VI "C" occurs with the 3rd out of the Sub VI 'A'. "

Is it true that Exit Sub VI 'c' using information from void VI 'A' that occurred 2 cycles earlier? If this is the case and I want to do real-time signal processing it will always be this delay in my final result?

If you could help me it would be sweet!

See you soon

In fact, Yes.

Tags: NI Software

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