Regarding UDP Rx. custom map FPGA for PC

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• FPGA for PC via UDP connection

  Hi all

  Background

  I am currently working on a project to interface an FPGA with a PC, to send a UDP load prepared on the FPGA for the PC. The FPGA is preparing a payload of 18 hexadecimal bytes from h00 8' to 8' h11 and then transmits it via a local network on port 1024, between the FPGA and a second network card in the PC, with static IP assigned to the second network card and the FPGA. Packages leave the FPGA and reached the PC (tested with wireshark) but the vi does not appear meet the payload and display it on the screen in the vi. The vi is based on that comes with labview and only has a few adjustments for most simply to write the final packages saved to a text file.

  Problem:

  Initially, when the vi was run the length of the chain kept evaluate to zero and so he perceived no bytes don't read from the port. I then inserted the flatten channel vi after the UDP read and before the comparison of string length (after reading something on the forum), now the length of the string is not evaluated to zero to 4 instead of this, I also changed the display to the spell option but the same 4 Hexagon keep coming through '0000 0000 0000 0D0A' , but they are not those who have been sent from the FPGA (are they an error message?) and not those taken over by wireshark. In summary, I seem to not be able to read the data of the UDP payload in Labview.

  I tested the VI locally using the Protocol UDP send labview vi and vi (slightly) custom receiver and it still works. The receiver that VI is attached.

  Any suggestions would be great,

  Thank you

  James.

  You can share the wireshark log (preferably in a format based on text that I did not install Wireshark)?

  Are you sure that is no firewall problem? If you are using a firewall, disable it completely for this network card or at least ensure that it accepts connections on UDP Port 1024.

  In addition, set the UDP sender VI on another computer and see if you are still receiving data. If it works, compare logs wireshark compared to what is sent by the FPGA and search for differences. If this does not work, then you have a network like a firewall problem.

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