Same code compiled for the cRIO-9074, but reports no diagram component calendar violation for cRIO-9067

Hi, just got my new cRIO-9067. I have converted my project over the cRIO-9067 since the cRIO 9074. Same layout module, same engine, same scan code custom fpga, (hybrid mode).  I have no problem of compilation for the 9074, which is a lower performance FPGA architecting the 9067 FPGA.

The final timetable for windows compilation shows that the timing is respected for all clocks - 40, 80 and 120 MHz (I use a clock derived for some code sctl). During the end of compilation, during the phase of gen bitfile, I get the dreaded time violation. Investigation of the breach indicates that it is not the custom code, it is not schema components. One of them seems to be linked to the card series OR 9870 I in the chassis.

Why? Is there anything I can try with the compiler directives for this problem? You would think that it would be easier to compile for the highest performance FPGAS...

OK, don't ask me how I thought this output - to run I changed nothing else than this: feed the I/O node a reference FPGA of e/s instead of configure the node via the menu "link to. It makes no sense, but the compilation succeeded when I did this.

I know it is because I created a very simple test VI in my project and made sure it does not compile without it.

Tags: NI Hardware

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