sbRIO-9651 IO corresponding length

We plan to interface high speed ADC (1gech/s x8bit) that uses a wide interface LVDS (two samples) from 16-bit to a sbRIO-9651.  Is there a resource that provides information about the sbRIO-9651 module layout details as worst case length offset series in differential pairs and between differential pairs that exist on the module (independent of our own layout of the Board of Directors)?

Since the interface use a common differential clock and wide 16-bit interface, I'm trying to get a sense tilt the worst case there might be between pairs differential seperatate.

I can they use sheet date architecting to get an idea of the maximum transfer rate, but are there restrictions on the module itself that will limit rates date?

Hi abadobid,

The SbRIO-9651 manual specifications (table 8) should have the details of length sur-module trace info you are looking for.

In addition, I recommend reading the Design Guide for the SOM carrier for detailed techniques, guidelines and requirements for the design of carrier card.

Finally, for future issues are the design of specific equipment for the SOM, we have implemented a dedicated community/forum that will probably be the best place to get help.

Community of developers of hardware for NI Single-Board RIO and module system

Resources for the system OR on the Module

Kind regards

Tags: NI Hardware

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