sbRIO frequency Max DIO
Devices former sbRIO receive a nominal specification for the 10 MHz DIO pins. It is documented in their textbooks. Does anyone know the most recent maximum frequency on mezzanine devices sbRIO 9605/9606 RIO interface? Their manuals are not yet validated.
Hi SolarSystemsLLC,
Please bear with us, as we are still working through final changes in the manual before post us it on the web. As mentioned in a previous post, the RMC DIO Andrew is directly connected to the FPGA through end of series of 33 ohms resistance and DIO are sent with a characteristic trace of 55 ohms impedance. There is no buffer online. With respect to a specification of the frequency maximum, DIO capabilities are limited by the components on a Board CTMR, the integrity of the signal between the FPGA and the CGR and any requirement of precise calendar request. In general, a typical SPI based protocol would be able to close the calendar with a rate of 10 MHz interface. If the application has no time limits between the lines, you will probably be able to switch or lines at a higher sample rate. As the design of the PMR is completely open, the signal integrity and timing of any design must be validated by the designer.
I took note to update this message when the manual goes live, you will be aware that his was published.
Kind regards
Steve Bassett
SbRIO-9605/9606 project manager
Tags: NI Hardware
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http://www.Intel.com/p/en_US/support
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http://www.Intel.com/content/www/us/en/blogs-communities-social.htmlI hope this helps.
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