Specified sample rate clock works do not

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  February 18, 2013 16:33 in response to talbot

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• Understand how to set up and use a sample FlexRIO clock

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  Following this discussion on inputs glitching, I learned that I need to use the area of the sampling clock to read nodes to HAVE it in my 5734 OR. So I right click 'FPGA Target'-> "New FPGA Base Clock" and selected "IO Module clock 0". In general, I followed the instructions at http://www.ni.com/pdf/manuals/375653a.pdf

  Issues related to the:

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  3. In the example of the FIDL, engine of CQI on 5734 SMU - 7962R.lvproj, 'IO Module 0 clock' is configured to be compiled to "100 MHz" instead of 120 MHz. is there a meaning behind this value? (# 1, I understand that the value is ignored)
  
  
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  1. In my current, more complex program, I get the same error even with disabled node, if I stop and restart the host VI - but the next attempt would succeed.
  
  
  2. I have attached the sample file project, the screw and bitfile, where they are useful.

  

  

  Hi FKSH,

  You are right that you must Access your e/s on the 5734 NOR in the area of sample clock:

  

  (this information is by using LabVIEW for the CLIP of 5734 OR)

  It is a clock Module e/s 0 or sample clock based on your version of the FlexRIO driver you have installed. Based on your statements, looks that you use LabVIEW 2014, so be sure to have FlexRIO 14.0 or FlexRIO installed 14.1. If you have FlexRIO 14.0 or earlier, the sample clock will be IO Module clock 0. If you have FlexRIO 14.1 or later, it will be the sample clock:

  

  (also of the documentation NOR 5734 CLIP in help)

  The only support for sampling rate is 120 MHz, unless you use an external clock CLK in and it must be between 50 and 120 MHz (see page 9 of the Manual). If you wish to purchase to 10 MHz, the best thing to do would be to sample the e/s to 120 MHz and then decimate the data by a factor of 12 (keep all 12 data points only and throw out the rest).

  Regarding the FIDL, I'm guessing that you're referring to the configuration in the properties of the clock:

  

  This configuration is not actually change the frequency of the clock. The compiler uses this value so that the logic can operate at the specified frequency, but the real clock is provided elsewhere (in this case, the FAM).

  Finally, I saw error-61046 occurs more often because of the configuration of the internal clock. Make sure you use the clock on the right as the only cycle timed loop source as I mentioned above. In general, I do not recommend write directly on a 120 MHz indicator, as there are a lot of other logic that needs to be done in order to update the indicator. The data are sent to a domain different clock under the hood, so you can actually update the data and I suspect that there are some conflicts with the clocks. You also lose data as the host won't be able to read all the data before it gets crushed. Instead, I would use DMA FIFOs if you need all the data you acquire or to send the data to a different loop which will be responsible for the update of the indicator in a slower clock domain.

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  Best regards

• DAQmxCfgSampClkTiming sampling rate for external sources

  I'm looking at the example of Synchronized_AIAO_Shared_Clock.c to http://zone.ni.com/devzone/cda/epd/p/id/2352 .  This example creates a string of tension that HAVE streams at 10 kHz, and then creates a tension AO channel that is bound to the sample clock HAVE to synchronize channels.  I use this example to understand the use of DAQmxCfgSampClkTiming here.  This is the corresponding code (comments are mine):

  Create a channel of tension HAVE will work continuously at 10 kHz

  DAQmxErrChk (DAQmxCreateTask("",&taskHandleRead));

  DAQmxErrChk (DAQmxCreateAIVoltageChan(taskHandleRead,"Dev7/ai1","",DAQmx_Val_Cfg_Default,-10.0,10.0,DAQmx_Val_Volts,NULL));

  DAQmxErrChk (DAQmxCfgSampClkTiming(taskHandleRead,"",10000.0,DAQmx_Val_Rising,DAQmx_Val_ContSamps,1000));

  Create a tension AO channel, and then attach the clock of the chain in tension of the AO for the sample clock HAVE
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  .. So what I'm trying to understand here is how to interpret (1000.0) sampling rate argument in the second call to DAQmxCfgSampClkTiming, where the canal AO is related to "AI/sampleClock.  It seems to me that this argument must be meaningless, other than perhaps to determine the size of the buffer, since by definition this AO channel will clock on a sample of every time that AI/SampleClock rises.  Then maybe someone can help me understand how this argument is used...

  But in all cases, the docs say "If you use an external source for the sample clock, set this value to the maximum expected rate of the clock."  In this case, the clock is set up a few lines earlier at 10 kHz, so is not this 'evil' in the second call to DAQmxCfgSampClkTiming, a sampling rate of 1 kHz is specified (much less than the maximum rate of sample expected)?  What is the consequence of this?

  Thank you!

  -Dan

  Hey Dan, some big questions you've got.

  You pretty much put the nail on the head with your guesses. The size of the buffer is based on the resolution of data acquisition in combination with the sampling frequency that you specify. Think of it as an implicit in the size of the buffer declaration (but it is certainly an explicitly define that, if you wish).

  As for your second question, which relates to new back to the size of the buffer, except that this time it is for the use of an external clock source. Given that the material has no implicit way to know the frequency of clock of this external source, it asks you to specify explicitly the maximum frequency so it can create a buffer of the right scale size.