The FPGA Module compatibility

Similar Questions

• Can damage the FPGA module if I connect accidentally two pins writing together.

  My current configuration has a PXI chassis with two FPGA modules.  Each FPGA module has an adaptation Module 6581 on that.  I would like to test the signal through my system path by having the user to move some cables that would be a reason for a return to the other looping FPGA.

  I fear, however, the risk of the user is not correctly as shown and somehow a channel available in writing that connects to another channel write-enabled.  This damage to the FPGA or adaptation modules?

  Hi Brian,.

  Your concerns are correct. We never want to connect two pins that are output voltage. If two pins are outputs digital mistakenly connecting them together may damage one or both nodes in output since there is nowhere to flow the potential.

  It is well to connect to two pins that read a voltage. If both pins running entry digital (reading of the pins), as there is no risk, nor pin would be likely to be damaged.

• No option to simulate the peripheral cRIO after installing Labview and RT/FPGA Modules of downloads (lack of driver support?)

  Hi guys -.

  Basically, I need to simulate a cRIO device without yet having equipment on-site, like this:

  How to simulate the FPGA hardware target using with LabVIEW Project Explorer

  Instead, I only get the options presented in the attachment "Add Target Options.jpg.  I guess it's because of missing drivers, which I assume is due to an error that I made during a recent new LV installation installation went like this: I downloaded (not diskettes) and installed the following (in this order, the latest versions all around):

  (1) LabView development system

  (2) real-time module

  (3) FPGA module

  (4) NEITHER-RIO (previous installation-by-installation)

  (5) DAQmx

  At the end of (1) and (2), I got the screen shown in the second attachment ("Drivers Installer Message.jpg"), but could not able to recognize the folder "device drivers OR" (I also downloaded), or one of its subfolders.

  According to me, I'm missing an obvious option to load the necessary drivers after installation, but can't seem to find reference to it in the forums.  Could someone give me a little help in the right direction?

  Thanks a lot and have a nice day.

  
  

• LabVIEW FPGA: An internal software error in the LabVIEW FPGA Module has Unknown

  Sir/Madam,

  Note Labview 2012 SP1 installed about 2 weeks ago.,.

  Accident occurred during the compilation of an fpga vi who worked satisfactorally in the past.

  When I restarted and went to the message recomplile "LabVIEW FPGA: an internal software error in the LabVIEW FPGA Module" see attached picture of popup.

  I reinstalled Labview in its entirety and backed out the changes I made to the vi but still get the same message.

  Thanks in advance

  Daryl

  It turns out that the question was in the VI and not of LabView FPGA module as the message may indicate. I created a vacuum vi, cut and pasted items in this from the vi error and recompiled and it ran very well.

  Somehow the vi has been corrupted internally.

  Thank you it's fixed.

• What is the use of FPGAS and how it differs from the IO Modules

  Hi all

  Maybe it's a silly question for most of you.  But I have very less knowledge about the basic concepts of electronic (FPGA, real-time) to cRIOs. I know that FPGA

  can be used to generate circuits within the chip that helps by some logical functions.

  I've just started working in the cRIO.  My question is that we have Modules e/s making it outputs all the application entry.  So, what is the purpose of e/s in the FPGA.

  Lets consider that we entered for an application of RTD.  In this case the module NI 9217 itself exits 24 bits of data from the RTD measurement which may be the process of the LabVIEW VI.  What will be this FPGA between the i/o Modules and the processor will help in?  Also I want to know what type of communication is used to send data between the FPGA and host modules.

  Thanks in advance

  Ajay HI:

  Sorry, you do not have an answer to your original question. However, you are right about the benefits of the FPGA. You said, if you build pre-processing in the FPGA, you can unload a lot of potentially CPU calculations out of the host processor. In addition, the program running on the FPGA is highly deterministic and can run the code very quickly. So if you build a kind of guard or evanescent dog part of your application, the FPGA is a good place to put it.

  To answer your other questions, communication between the modules and the FPGA is generally above the SPI and the data can be transferred between the FPGA and host via DMA FIFO operating on the PCI bus or single point save access using read/write in the FPGA host Interface controls. You can also use interruptions in signal of disputes between the FPGA host.

  I hope this helps, but let us know if you have any other questions.

• Cannot send DIO siganl using the LabVIEW FPGA Module and MyRIO

  Everything works when no FPGA is used. If the circuit and harware work.

  However when targeting module FPGA MyRIO, acquiring data and processing the work and the signal to the engine's 'sent' (visible when executing Hightlight is on).  But there is no tension on the DIO ports used. FPGA projects includes VHDL code.

  Do you know what could cause this problem?

  You must control the OID in the FPGA.

• How many modules NI 9505 can I program the FPGA (with SoftMotion) NI 9104?

  Hello.This is my first question here. When I try to make the FPGA code to four NI 9505 (with loop position (including SplineEngine), current loop, loop PWM and encoder loop) I simply double code for module four times. I use the NI 9104 chassis with 3 m doors, but compiler returns compilation error (I guess, code does not fit on FPGA). I tried to make the code more simple (I combined some terminals). But it did not help me. Thanks to lot.P.S. sorry for my English.

  This message may be a bit delayed - but I did a lot of work to obtain many 9505 modules compiled on a number of different FPGA targets. Seven on a Virtex-II 3 m gate FPGA and eight on a 2 million doors Spartan3 (don't be fooled by the size of the door - the Spartan FPGA tends to be more effective in the compilation of size, but the worst with a timing compared to the Virtex II. The Virtex5 are better all around).

  They key is "mulitplex" code - in particular the SoftMotion contructeurs algorithm. Multiplex in this sense means both use the same code for each axis and process things in series parallel vs. Because the constructor requires the backup of important data for each axis between the loop itterations, use of these VI block of RAM on the FPGA vs using large arrays in FPGA fabric.

  I have attached a code that will work with LabVIEW 8.6 and SoftMotion 2.2. This will NOT work with 2009 SoftMotion (RT both the FPGA VI changed).

• Error-63101 when executing the FPGA Interface C API Generator in LabVIEW 2012

  I'm using LabWindows CVI 2012 and 2012 LabVIEW FPGA module.  I try to use the FPGA Interface C API generator and I get the following error from a freshly generated .lvbitx bitfile.  I use the local server compiles on my PC.

  Error-63101

  NOR-RIO: A valid .lvbitx bitfile is required. If you are using a valid .lvbitx bitfile, the bitfile maybe isn't compatible with the software you use. Determine which version of LabVIEW was used to make the bitfile, upgrade your software to this version or later, and then try again.

  The problem occurs when executing CVI or LabVIEW.  I was able to do this earlier when I was compiling the FPGA in LabVIEW with the API generator 2011 downloaded from the Web site.

  A bit of weirdness in my setup, it's that I charged it off downloads from the website (latest files after 2012 NIWeek) rather than the normal distribution DVD.  I installed LabVIEW, so NI RIO, then the Xilinx tools compatible with 2012.  It works very well when you talk to the FPGA to a LabVIEW vi running on my Windows PC to the host.

  Any suggestions?

  Problem solved.  I had to download FPGA Interface C API generator 12.0.  It works now.

  I would have thought that if a product was called on the menu in LabVIEW 2012, it would be prompted to upgrade to a compatible version, when I installed LabVIEW.  The old version is not compatible with version 3.0 bitfiles, as identified on the following lines at the top of the .lvbitx file:

  
  
   3.0

• 24 v digital signal of the event from the host to the fpga power on/off

  Hello forums or

  Sheet material

  cRIO-9074

  module or 9472 digital module 24 V output c series

  To expand on the topic described,

  I want to be able send a trigger to alarm the fpga digital 9472 out that lasts 30 seconds using the operating system time real clock time on the host computer

  The way I approached this problem is that

  In the loop where the event occurs, if the event trigger is defined then the fgv has a time stamp when the event occurred is sent.

  In the loop that communicates with the control of fpga, I write to the control based on the condition that the difference of the current time checked and fgv time is 30 seconds or less, then it will send the value true, otherwise send fake and wait for the next occurrence of the event.

  The main problem after implementation of this is that 9472 led does not turn off when the false value is sent to it.

  cordially Mzamanstl

  Timer Keeper SD is a FGV so that it is written for her, once the event occurs

  So if the event occurs so timestamp is stored and then the difference of the timestamp result is<30>

  then a true value will be sent to the module of 9472

  So basically I want the light and I want to do the 24 v output for 30 seconds then turn off and wait for the next occurrence

  I think the method that I test it with is not very good, because I realize other factors that may contribute to this problem, so I think I found another way to test

  and I will try it but its will take time.

  cordially Mzamanstl

• Broken the FPGA VI but the empty error list

  Hello!

  I'm trying to run a vi which includes a 'Open FPGA VI Référence' function. However, an error and it says that "not compiled FPGA VI. When I try to compile the FPGA VI a message saying "The VI is broken". I try to run the FPGA and when appears in the error list, there is no error or warning in the list, although the name on the fpga includes the Red 'X' ('show warnings' is checked). Any help?

  I'm using Labview 2013.

  Pablo

  Hi Pablo.

  Sorry for my delay in responding, you managed to get the respected FPGA.vi yet?

  To answer your questions, if the project is ok with an empty FPGA.vi, then in theory, your hardware is configured ok. However, due to the vi being blank, you haven't tried to use one of the modules on your system, so it can introduce errors. The most common mistake is differentiation of mode Scan Mode/FPGA by installing the project in the first place. Also be aware that not all FPGA targets supports everything, for example some dislike for the rows that have an index to calculate the number of iterations, rather than a constant wired at the entrance to "n".

  Out of curiosity, why you place every measure in the DMA separately and also specify address? Is there a reason you don't just place all the measures in a table and put everything in the DMA, then divide the table on the other side?

  Generally speaking I don't think that incorrect programming should never cause LabVIEW crashing and you should always report the problem to the OR in order to take a look and see if they can fix it.

  Hope that you managed to get your problem sorted and again sorry for the late reply.

  Darren.

• Internal software error of LabVIEW FPGA Module - 61499

  I get the error next (in a pop-up window) in the phase of sompilation for the FPGA target with a vhdl IP. This error continues to occur even after restart LabVIEW and the PC. Someone at - it solved is this kind of problem before without having to re - install the software?

  Here is the error information:

  Error-61499 occurred at niFpgaXml_GetValue_String.vi<><><><>

  Possible reasons:

  LabVIEW FPGA: An internal software error in the LabVIEW FPGA Module has occurred. Please contact National Instruments technical support on ni.com/support.

  Additional information: lack the tag required XML (/ CompileServerList)

  As a first step, I can compile the vhdl IP node successfully. However, once when I'm running a VI with the FPGA, the bureau stop working. After that I restarted by force, it cannot perform the build of a vhdl IP node. Even without connecing to the jury of LabView, he pointed out errors before the end of the sompilation.

  Interestingly, the screw which also includes nodes IP vhdl that I properly compiled before, I can still run the VI to the Commission and it works correctly.

  Thank you

  Looks like your ActiveJobsList somehow has been corrupted. I saw occur when computers are hard stop or blue screen during compilation. I don't have that LabVIEW 2014 installed on my machine, so your path will be a little different, and the file extension will be a .txt or .xml instead of .json, but try this:

  Move the file "C:\Program Files (x 86) \National Instruments\LabVIEW 2014\vi.lib\rvi\CDR\niFpgaActiveJobList.json" (or your equivalent) out of the above directory (back it upward and delete essentially) and restart LabVIEW. Must regenerate the file and resolve the problem.

• How to get a lvbitx, which is already compiled on another PC, installed on a new FPGA module (similar) 9146 (without recompiling).

  Hey all,.

  How to make a lvbitx, which is already compiled on another PC, installed on a new module (similar) FPGA 9146 (without recompiling).

  I gave only the lvbitx, not the entire project file.

  Can someone help me with this?

  Thank you in advance.

  What you compile the file bit for?  Also a 9146?  You try to use the file bit with the same version of LabVIEW?

  If it's the same type of target and the same version of LabVIEW (or its execution engine), and then you call just the bit with the FPGA VI reference open file.  Otherwise, you will have to recompile.

• The FPGA IO corresponds to which C-series e/s?

  I have a PXI-7813R with connectors 0 and 3 connected to a chassis with modules of series C in them (9474, 9205, 9206 and 9423).  I want to know that I/O corresponds to what e/s on these chassis.

  As far as I know my FPGA project (which was written not by me) are the channels of each module of the series C are used, but I don't know what DIO channels they correspond with on the FPGA.  For example, I can use the 9205 channels 0-31, but that channels 68 connector 0 of FPGAS which corresponds to?

  Does anyone know how to tell you this?  Thanks in advance.

  joedowdle wrote

  I want to know that I/O corresponds to what e/s on these chassis.

  Why do you ask that? When you use Connector0 to the expansion chassis, the Connector0 IOs are more available in the project, on the contrary, the expansion module chassis and can be configured as explaind here. Also take a look at this thread.

  Christian

• I want to run an engine using the FPGA card 7851r 9474 C Rio 9151 pilot control is possible or can I do in LABVIEW, CVI

  Hello I want to run a Stepper with 7851 FPGA R card with driver 9474 crio chasis, but I'm not able to understand how to proceed. Or may choose this option by using view lab CVI

  Hi VHS.

  first of all, I would recommend that you want to use materials. Basically, to control a stepper motor, you have a controller of axes and a player.

  In fact I don't know why you want to use 7851 R card and cSeries 9474 module. In any case, you can connect the FPGA Board with an NI 9151 expansion chassis for

  Plug the 9474.

  In the following link, you will find basic concepts on control of engines with NO motion:

  Motion Control fundamentals

  http://www.NI.com/white-paper/3367/en

  In addition, you need a software application. NEITHER offers LabVIEW - graphical programming and LabWindows CVI language - it is a system of development in C-ANSCI

  for C programming.

  Kind regards

  RupiDo

• Download NI LabVIEW FPGA Module Xilinx Tools 10.1 2013 problems

  I'm trying to download the Xilinx tools 10.1 to use with a chassis 9113 in LV2011.  Based on this white paper, that the compiler below should work perfectly.  The problem is that I can't seem to download all the way.

  I can't seem to cross ~ 336MB using the standard or the downloader OR.  Any ideas?  Does anyone else have this problem?

  http://www.NI.com/download/LabVIEW-FPGA-Module-2013/4249/en/

  Thank you

  -PBD

  Well well... on the good side of things, you don't want 10.1 anyway!

  

  Virtex-5 LX50 FPGA<- requires xilinx="">

  10.1 is only for devices FPGA Virtex-II! (.. .after LabVIEW 2009 it was, just for all of you who read this know).

  so... try this link: http://www.ni.com/download/labview-fpga-module-2013/4248/en/