The SoC Xilinx architecting 7010 is added to myrio, my question is why? Which task is done by the CPU and which task is performed by the FPGA in myrio when running LabVIEW.

Looking myRIO Xilinx architecting-7010 SoC I am bit inntrested in the workflow for the GS. How does the bennifit myRIO use a system on chip instead of a regulare CPU and FPGA not in the same chip.

4 way could there be to manage a VI?

With FPGA and RT (CPU)

Only of FPGA

Only RT

only the windows

I am comfused, is it any good article/doc describing this?

I found the image in a PowerPoint on the www. -What the task split like this betwheen the CPU and FPGA?

Hello

Please see this link. This can help you understand the architecture of RIO, and there are many whitepapers available in ni.com

Tags: NI Products

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