Transmission of data to the host of RT to the FPGA via DMA FIFO

Hello

I try to write data from a host of RT on target FPGA using DMA FIFO and then process these data and read then return of the FPGA target to the host of the CR through an another DMA FIFO. I'm working on the NI SMU chassis 1062 q, with the built-in NI SMU-8130 RT controller and target FPGA NI SMU-7965R.

The problem I face is that I want to send three different tables, two of the same size and the third with different size, and I need one more small to be sent first to the FPGA. I tried to use encode dish with two executives in the FPGA VI. In the first image, I read and write the first table in a while loop which is finite (that is, a finite number of iterations). The second frame contains the process of reading and writing the second two tables (of the same size) in a while loop that can be finite or infinite (depending on a control). The problem is that it does not work. 2 arrays are displayed on the front panel of the RT VI host and works well, however, the table that should have been read in the first sequence does not appear on the front panel of the RT VI host. It is not sensible because if it is not passed from the host to the fpga and vice versa then the second image should not have been executed. Note that I'm wiring (-1) for the time-out period to block the while loop iterations until the passage of each item is completed. So the first while loop has only 3 iterations. Could someone help me undersdtand why this happens and how to fix this?

I enclose a picture of the host and the fpga vi.

Thank you.

If you vote for my idea here and it is implemented, you can even omit the loop FOR fully.

(I also propose the RE / IM divided inside the loop FOR and perform operations on complex table before the loop the transpose and reshape .) In this way, you only need one instance of these operations. You might even save some unnecessary allocations table in this way)

Tags: NI Software

Similar Questions

  • Problems with the transmission of data between the screws

    Hi all.

    I have a question where my program slows considerably during the race.

    The program is a producer-consumer, where I have the main consumer loops and loops producer for USE comms, measure the output power, input for measuring the power, thermal control, etc..

    Regarding the issue, the measures of output loop takes readings and transmits the data to a separate VI which remains running (measure of output processor). This VI summarizes and on average the data and also displays data for the operator to see details if necessary. The operator shows and hides the front panel of this VI with a button on the main program. This VI also returns the summary data to the main VI, where it is read by my loop of consumer.

    The main measures output VI loop takes about 200mS to run when the program is first started. Less than a minute, it is 400 MS, and it's all downhill from there.

    I've isolated the problem to the way I pass data back (I think). I couldn't find a way to pass the reference of the queue between two screws not connected by wires. I open a reference to the VI processor and use Ctrl Val.Set and Get to pass the data back. If I take the intersection of the Subvi data, there is no slowdown.

    My questions are:

    (1) why the data passing by invoking a node of the control on the target would cause the downturn?

    (2) how would I get/pass information of queue between the two screws are not connected?

    (3) Alternately, could I start the VI processor in my main program, run and pass data in and out of it? I want to keep it running, because it is also part of the user interface.

    I don't know that I have not explained this very clearly. I took some screenshots of my code, but don't see how to download here.

    Thanks in advance,

    Jim


  • How data for chart FPGA of DMA Fifo and relaxation

    Have a design Question here:

    IM using a FIFO DMA here at the flow of data from the target to the host.  Side host, I was using the FIFO read Functinon, converting to Dynamic Data and display in a chart in 'real time '. Pretty easy.

    However, I would like to make it more functional.  The incoming signal is essentially a square wave.  I want to trigger on a rising edge, and then graphic permanently the result in the table.  I tried to add that 'trigger and Gate' express Vi, but its uneven (see attached photo).

    I am on the right track, or should it be done differently?  I was not able to find specific examples for this.  I think Im getting messed up because my data are read from the FIFO as a table 1 d, 5,000 items at a time.  All of the other examples I've found just show the signals that are generated on the host computer already at a fixed frequency.

    Thank you!!!

    Bones349,

    Hello! Some ideas/questions

    1.), you could make a detection of edges in your FPGA, saving you a lot of treatment because no no need to spend no relevant data until the host code.

    (2.) what you're doing in splitting the numbers before their conversion to the type of dynamic data? I'm not surw what happens there. You can use a data type of waveform instead, because she would have an element of time to your data.

    3.) 5000 incidentally both through your FIFO would be fine.

  • What would be the effect of the adjustment of the depth of DMA FIFO before every read?

    I'm using a PXI-7813R FPGA board using a 3rd party API. I had a few problems during playback. I looked in their API (LabVIEW) code and realized that they were in DMA FIFO depth before each reading of the FIFO. This apparently does not cause a failure of catastrphic issues I have observed are only transitional in nature.

    What kind of problems, if everything can these operations cause or will be ignored because the FIFO is already running?

    Thank you...

    mgerceker,

    According to the help file , that should be OK to do even though I could see it being a problem if it is not set correctly before performing an operation. What kind of symptoms do you observe?

    Greetings from Austin,

  • Transmission of data between the clarification of the screens

    Hi, thanks for taking the time to help

    This issue has been raised before. But he never seems to be a direct response to this problem.

    I have two screens. The first screen has a button and a LabelField. The button pushes a new screen with a timer on this subject. I'll start the timer on the second screen. Now, I want to pass the value of a that time, as a string, return on the first screen to be placed in the LabelField.

    May I ask, how can I do this please?

    PS. is it possible to pass by reference in Java... I'm a newb as you may have guessed.

    "This issue has been raised before. '" But he never seems to be a direct response to this problem. "

    "I am a newb as you might have guessed."

    I think that these two points are related.  In other words you don't know how to do what you want because you're new to Java.  And for more confusion, there are at least 3 different ways to do it.

    One way is to static variables, as the previous poster suggested.  I personally would not recommend that approach, as for me using methods and static data is kind of anti paradigm object (at least it seems that way to me).  Just it's just personal.  YMMV.

    Think in terms of purpose, at its core, a screen is just an object.  It is understood by the system to provide an intervention of the user interface, but it is above all an object.  A part of the question you ask here is:

    "I have two objects.  .... Now I want to spend a time value, as a string, the second object, the first object. »

    A simple answer to this question is to use a ' getter '.  If 1 object creates the object 2, then an intervention takes place 1 item then gets the value of the object 2.

    So that's part of the problem solved, in a friendly manner of the object.  Now the second part:

    "The button pushes a new screen with a timer on this subject. I'll start the timer on the second screen. Now, I want to pass the value of a which time... »

    I assume that you need not the return value in the Second screen until the user has closed the second screen?  In this case, when you tap on the screen, use pushModal.  Then the control is returned to the statement after the pushModal when the second screen is closed.

    Now the third part of the process:

    "to be placed in the LabelField.

    If you have a reference to the LabelField, then you can 'set' the value you have in the second screen using your getter.  This code would run after the pushModal.

    Job done...

    Other variations on this include having 2 screen be a reference to the display 1 function and update the value directly.

    But my favorite is not having the data in a Screen object.  Have a data object that contains the value of the timer, have getter and gets of the setters on this data object then Screen2 sets and screen 1.  Both screens are in need of a reference to this data object.  But the big advantage of this approach is that if theer is Screen3, who also wants to see this same value of the timer, so it can be given a reference to the data object and all three screens will see the same value, because it is the same value, without effort.

  • transmission of data in the url, what happens if no data is transmitted

    I work in php with MySQL.

    Some pages of my site require certain data to be passed in the url. In most cases, it is "data_region". If this is not passed in the url, I get an error of "undefined index". Is there a way to tell:

    If "data_region" exists, use the information that it passes.
    use else '? data_region = ALL'

    Right now I use a web redirector on the index page to the main.php with the correct data_region instead of having main.php as the index. It's OK, but it sometimes takes a while, especially on slower connections.

    Any help appreciated.

    My code:

    deadlyhifi wrote:
    > I don't see what you're trying to do here, but it does not work because it is
    > looking for '? data_region' in the URL. I need to apply
    > 'data_region = ALL' when 'data_region' is not mentioned in the URL.

    In this case, put this at the top of your page:

    If (! isset($_GET['data_region']) $_GET ['data_region'] = 'ALL';)

    --
    David powers
    Adobe Community Expert
    Author, "Foundation PHP for Dreamweaver 8" (friends of ED)
    http://foundationphp.com/

  • How can I transfer more 64-bit data to the target host?

    Hi all, I currently use fpga PCIe-7851r card to drive my camera. There were 64 lines to remotely control. So what I did generates the commands on the host pc and transfer it to the target via DMA FIFO. The data type of the FIFO is U64, i.e. each digit control 64 DIO lines. But the issue becomes complex when I transfer 66 command-line. I tried to create 2 FIFOs, but I can hardly do the 2 Sync FIFO.

    I think I might be able to create 2 tables U64, one contains the original 64 line, s command and the other for the 2 line (a loss) information. And then I have them interleave in hospitality and decimate them in the target. There should be enough cycles to it. But I don't think it's a good solution. Is there a better method? Thank you.

    LabVIEW 2009, Windows XP, PCIe-7851R

    Kind regards

    Bo

    Using the techniques highlighted in this tutorial:

    http://zone.NI.com/DevZone/CDA/tut/p/ID/4534

    You can use code like this:

  • How is managed using DMA FIFO (target host) host matrix

    Hi people,

    I'm trying to pass an array of values of the host to the FPGA using DMA FIFO. Let's say 20000 items in the table. My FIFO host side can contain only 16000 items or almost. The data will be written element by element regardless of the size of the table or do I need to partition the table in small paintings before writing the FIFO method? Let's say that I write for the FIFO with berries small, 1000-element. The FIFO will read 1 element both of the side FPGA so the stream is blocked until I have at least 1000 free items on the FIFO method write, how he writes every 1000 the next setpoint at the same time? Or target values will be written permanently as soon as the individual elements are erased by the number of available items to write?

    Hi Nathan,

    Sorry for the late update, but I just thought that I should follow. I followed your advice and try it tested just for me (I probably should I have done it before posting). Turns out that the data table will write even if there is not enough empty elements to contain the table in its entirety. However, it always crashes until enough information is read and erased from memory on the side FPGA for the whole table. So if it's data that are constantly being played, it's always better transmitting data through in the form of smaller tables if you do not want to increase the amount of memory FIFO host OCCUPIES on your system. However, if you can afford the memory while you mentioned, you can always increase the depth of the FIFO on the host side. As I understand it, try to write more big berries to a host to target FIFO buffer does not diminish overhead costs (as is the case with a target to host FIFO) as it still passes an element at a time to the FIFO of FPGA-side without worrying.

    Thanks again for your help.

    Kind regards

    John has

  • How to save data in the text file of Spartan 3

    Hi all

    I would like to kindly save the data table text file or a spreadsheet on vi using fpga spartan 3e as an fpga target. Once I added all the functions related to the operation of file, it gave an error that these functions are not supported by the target device.

    could you please help me with this

    Thank you

    Rania

    Hi David,

    Thank you for posting. You use LabVIEW? If so, what version of LabVIEW FPGA do you use? You use a host VI, or any deployment of code at your target to run? The file IO VI probably won't compile to target because they are not intended to be used on your host computer. Resources and the paths of files do not exist on the target FPGA, but rather on the side of the host. I have included a link below that describes how to transfer data between the FPGA and host. I hope this helps!

    http://zone.NI.com/reference/en-XX/help/371599F-01/lvfpgaconcepts/pfi_data_transfer/

  • Communication problem between the FPGA VI and VI host-PC

    Dear Sir

    I am trying to establish a communication between a FPGA a PC host using the FPGA FIFO.

    The communication still has a few problems and I do not know what cause them.

    LabVIEW gives me the following reason "transfer has not completed within a stated time period, or in the specified number of retries."

    What is the problem with my labview program? How can I solve this?

    The project are attached.

    Best regards

    Beurms Jasper

    Hello, Jasper.

    Based on your feedback that a good approach might be to use DMA FIFO of the FPGA on the RT controller and use the network stream to send all on the network.

    Please note that (based on your original code), may also be useful to take a look at the use of DMA FIFO with interlacing.

    PS: I mention this because there is a limit on how many DMA FIFOs, you can use onach RIOtarget.

  • DMA FIFO (target host)

    Hello

    I have the next vi FPGA and RT vi (joint). I'm trying to transfer data from the FPGA to the RT vi (using the target to host DMA FIFO), then to plot the data in the RT vi. The signal that I take analog input also is a 10 Hz, 1 well module 9215 V sinusoidal amplitude.

    However, in the RT vi, I get only one exit fluctuating, with only the values 0 or 1. Also I see no time-out that happens with the RT parameters vi as: 'TimeOut = - 1' and "Count (uC) = 25".

    Why would this be happaning?

    Thanks in advance...

    Mandar-

    Hi Mandar,

    Not with 8.6. You told me 8.5 documentation (I didn't know you were using this version). Take a look at the following article; It should solve the problem that you are facing:

    How can I transfer my data to fixed-point using a FIFO in LabVIEW?

  • Target to host DMA FIFO not compensation when they are arrested

    I use a PXI-7841R (Virtex5) and 32-bit data to the host via DMA FIFO transfer. When you read the FIFO on the host for the first time, the data are "stale" (which means that it is not what is currently coming in the FPGA, but what came in a few seconds ago stale). I tried both a stop and a configuration for clear memory FIFO before I use them. Documentation on one or both of these so-called clears the target and host the FIFOs. Does not help in both cases. With readings of the second and the following, FIFO has then 'valid' (same data as it appears on the FPGA entry node). What is curious is that each reading exactly the same thing:

    1. Stop the FIFO (must erase all data)
    2. Elements of reading 375 of the FIFO. (repeated playback of the FIFO)

    Also interesting: FPGA FIFO is implemented for 255 elements. The first 255 items host-side contain the data "stale" on the first reading. It reminds me of the never erased FPGA FIFO.

    Answered by support OR. The documentation for the FIFO, stop and configure FIFO is in error. Cars of documentation will be written against them.

    Solution:

    These methods remove only the FIFO on the side host. Data FPGA FIFO must be read following until no element.

  • DMA FIFO of FPGA to host RT is full

    I transfer data via DMA FIFO of FPGA to host RT.

    DMA FIFO is full, I have tried everything I know:

    -increases the size of the FIFO DMA up sideways FPGA

    -set the depth of the FIFO DMA to 100000000

    -increases the amount of DMA FIFO reading in each iteration of the loop

    -use a timed with a frequency of 1 MHz, instead of a normal life all loop

    Please find attached my project folder, FPGA code and code RT.

    I solved my problem.

    Below you will find my FPGA code before solving the problem and after resolution of the problem.

    Solution: I just added a function of 5000 milliseconds (5 seconds) to wait before getting the analog input nodes samples (AI).

    Before:

    After:

  • Effective use of the FPGA read/write

    I am writing an application for a CompactRIO real-time and I am looking for ways to simplify my code and reduce the CPU usage. I use FPGA to do much CAN e-mail and signal processing, then I have a VI running on the real-time processor that reads values in the FPGA, does some processing and outputs data in the FPGA. My code running on real-time parallel uses several loops running in a master/slave architecture. A single loop reads all necessary information in the FPGA in indicators and writes the values of the controls in the FPGA. The other loops read entries and manipulate the outputs via local variables.

    My question if it would be more effective to get rid of the loop which is dedicated to the communication of FPGA and has of each loop to read and write directly on the FPGA. If I use a reference block FPGA open and use the reference of the output in several loops, each read/write operation block others until it's over? Each output is changed only in one place in the code, but there are several entries that are used by multiple loops. It is even more effective for each loop of read/write for the FPGA on request? How will this affect determinism?

    Thank you

    Jon

    Jon,

    Read/write controls is not deterministic, but I think that your previous method should work just fine, as long as you have that unique writers. If you have multiple writers, you start affected by race conditions.

    I don't think you will see a significant improvement in the performance/CPU in the alternative method. You would see big performance gains if your master loop reads more slowly indeed, but it's always a compromise.

  • For a DMA FIFO running from the host to the 7976 is a data type that is optimum for PEP?

    For transmission to the host 7976, I can pack my data in say U64s or break up in U8s.  Y at - it a data type that will give the best rate?  Maybe based on the bus (SMU) or the implementation of RIO drivers behind the scenes?

    My experience is different.  Once, I did a load of tests with different widths DMA FIFO for FPGA and tested the throughput and latency.  If sending data via U8, U16 or U32 DMAs, I saw the same total transfer of bps.  My explanation for this?  Given that the width of the DMA is 32 - bit, LV little packaging in order to ensure that each part of the 32 bits is used.  This means that if you have a DMA U8, it will transfer at a time, 4 to DMA 2 both U16 or U32 DMA one at a time.  64-bit is divided into two individual transfers.

    Do not use FXP.  Even a 1-bit FXP is represented internally as 64-bit and will require TWO DMA transfers to an FPGA.

    Side fromt hat, U8, U16 or U32 makes essentially no difference because they are all packed 32-bit internally.

Maybe you are looking for