Violation of compilation-Timing error FPGA

Hi all

I've been LV around for years, but I am a complete newbie when it comes to FPGA. I'm working on programming for a 9651 (SOM) using the Dev kit. I'm starting by small steps, but already tripped. I have a simple VI which retrieves a value from a FIFO and passes it réécrirait a different FIFO. When compiling, it gives an error of timing violation, and I don't know how to study. The VI is attached.

If background for the curious... I'm working on the side of our application to signal processing. I'm passing data from a prerecorded TDMS file to a FIFO. I want to send the FPGA, treat it and send it back. Eventually, it will come of I/O, but for now, I just want to work on the processing of the signal. Before starting work, I thought I'd just make sure I can transfer data to the bottom and back. Once I get this job, I'll start to developing processing screw for between the two.

Thank you!

Hi thutch79,

You can specify the version of LabVIEW you use and implementing CLIP half bridge that you use for the IO DevKit?

It was a timing violation introduced between LabVIEW 2014 and 2015, given the way the compiler Xilinx handled VHDL which takes in charge the second port Ethernet on SOM.  If you use a CLIP half bridge that has been generated before 2015 LabVIEW (as the example of the expedition which I think begins with a CLIP called "DevKit"), then you can get a timing error.  There should be a second sample CLIP called DevKit2, I think, which was regenerated with compatibility for 2015 of LabVIEW and later versions.

This problem has been discussed here:

You can check your half-bridge CLIP in the project by ensuring that you have selected the version called DevKit2 if you have a version of LabVIEW FPGA which is 2015 or newer.

Kind regards

Tags: NI Software

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