What is the relationship of synchronization between the input MUX and the clock to convert DAQmx

My application requires both long settling for the analog input.  I can slow down the clock to convert in order to increase the interval without but I would like to learn more about the internal synchronization and synchronization between the switching of input MUX and the clock to convert.  Data acquisition is USB-6225.

Thank you

Neville

wet'nwild,

You have reason in the observation that hold all the impulses of the event happening 180ns after convert rising edge clock, regardless of the period of the clock to convert.

This is the process:

1. the clock Convert generates an impulse to start the ADC conversion.

2. a period of time (in your case, 180ns) after the clock pulse to convert, the complete signal hold impulses. This indicates that the data are "required" by the Active Directory Connector. It is now OK for the MUX switch to the next channel. It is important to note that the ADC conversion is not complete when the pulse hold full occurs.

3. at this stage, the MUX will pass and the device will wait for the next clock pulse to convert for the start of the next conversion.

In summary, this means that when you change the period to convert clock signal, the complete signal hold flashed always the same fixed amount of time after the edge of signal clock convert. The complete signal Hold'em is not a good indicator of break-in; the width of the period to convert clock must be waiting time indicator (which looks you determined you're previous posts). A good application for the signal keep complete would be for an application where there is an external multiplexer and the multiplexer needs a signal indicating that it is OK to switch the inputs.

I hope that helps clear up any uncertainty that you have about how it works!

Kind regards

Aaron

Tags: NI Hardware

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