Why do I get the compile time extremely long with FIFO on the cRIO-9073?

I use a cRIO-9073 to develop a data acquisition system.

When I try to use a FIFO to pass data to the host the FPGA, I get extremely long to compile (hours!).

Currently, I use that a single analog input of a module 9205 in my loop FPGA.

Y at - it an explanation for that?

Thanks for any help you can provide.

Michel

Paul,

Thanks for your reply.

I finally found the problem: the size of FIFO, I requested in the properties of the FIFO was too large to 32K items (for the type of data the FIFO U32) 4 times. He was filling the FPGA, 128 KB of RAM completely, leaving no room for manoeuvre for the compiler for the remaining logic. So bad, there was no warning for that!

By reducing the size of my FIFO at 4K, the compile time came in 5-10 minutes instead of hours!

Michel Lanthier

Tags: NI Software

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