Why extend a timed loop always expands diagram in the same direction?

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  I place two same while loop in the block diagram, and then use highligt and one-step run function to observe their parallel operation.

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  Can someone help me understand this?

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  Hi, GerdW

  Thanks for the reply

  I post a video to illustrate my question.

  While I press a strong of the run, I find that these two loops does not begin at the same time.

  While the execution of a loop, the border on the other became dark.

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  I do not know why this happens

  Sincerely

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• Schedule iteration five FOR lines inside a timed loop...

  Take a look at the attached code simply run five different but identical TO the lines inside a single loop timed.

  It is interesting to note the timings of each loop iteration FOR: 1,1,2,3,0 milliseconds. The most curious is the moment of the last loop, which for the most part indicates 0! Not only this, if you remove the fifth loop, the fourth a bed 0.

  I can't understand this behavior? Also if LV deals in parallel different loops why should there be a gradual increase in the synchronisation of successive loops?

  Thanks for any help.

  First, 0.2 ms is not statistically significant, you must increase the number of iterations by another factor of 10, at least.

  A quick loop uneducated wait FOR will grab the CPU for much more than one iteration, so regardless of the loop is first online will repel the other loops and run until LabVIEW decides to switch to another loop. The number of cores CPU do you have?

  You can force a release after each iteration by placing a 0ms wait inside each loop FOR. While all time will be significantly longer because of the overhead of increased switching, all loops will be now around the same time.

  You can also read this for more information.

  I don't know that anyone else can provide more details in the jargon of right. I don't know the correct terms for all this.