Why SPI participates with clock select on 5761/2 scanners?
The CLIP reference for the 5761 5762 sample clock commit signal States, and "when going from FALSE to TRUE, updates the sample clock according to the settings defined by the signal of selection sample clock." Shipping examples bookends the rising edge of clock sample commit with SPI Idle check. Why the SPI is involved with setting the sample clock?
Thank you
Steve K
I have a requirement to PLL to IOModSyncClock, so if SPI become inactive within the time limit, should I give up? In other words, if SPI will not idle 10 ms after the rising edge of clock sample commit, so I am not locked (for example clock select = IOModSyncClock lock).
I would not abort, rather I'd throw a significant error that allows to recover gracefully or stop the execution. Otherwise, it seems that you have the correct impression on which should involve the remaining false SPI Idle. However, I think 10ms sounds a bit too short. I'd go with at least 100ms, probably closer to 1 s just to be sure. If it takes more than 1 s, then you can assume that something has not been configured correctly before you start setting the clock.
Tags: NI Products
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