Why the output signal is pulled up to stop the program in RT

I use 9401 output a PWM signal. When I run the program FPGA and the stop, it does nothing statement. BUT when I run the program through RT using the compiled bitfile and stop, there will be a high level of 110ms.

Here's my diagrams FPGA and RT of a simple signal output.

I wonder why this could happen? Should I observe all specific during the programming of the RT?

Thanks in advance

You can add logic to ensure that the output goes low when the judgment is TRUE within your unique Timed Cycle loop.  My guess is that you just see a delay between when the FPGA is ordered to stop and when the file bit is actually closed and the FPGA is reset.

Tags: NI Software

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