NI Products

Open workspace tool

Hello I am trying to open a workspace tool of Labview Veristand as described here: http://digital.NI.com/public.nsf/allkb/77A8EE353C9E461B862579E9006891F7 Although the windows in the workspace opens (which means the project ref is correct), I get a n

VeriStand "Custom Device" creation, including the different types of sources of code for simulation only

Hello Before I ask my questions, I want to describe my problem: I would use VeriStand on a PXI system for simulation only. The simulation includes different types of sources such as Maltlab-Simulink-models, MultiSim SPICE models and code LabView for

Cannot deploy when you use the FPGA configuration file

Hi all I'm new to NI Veristand. We use a controller NIPXI 8108 with a map of FPGA OR 7841R. Is the used chassis OR PXI 1042 q. VeriStand does not deploy, when we try to add the target FPGA. For adding, we used the default for NOR 7841R provided with

Settings/discontinuity of SineWave

Hello Is it possible to have two sinusoids that play one after the other would accuse discontinuity? I know that I can can use the setting Phase and calculate as follows: y = Amplitude_A * sin (frequency * time + Phase_A)Bias_B = Amplitude_A * sin (f

Date and time display on the workspace

Is it possible to display the date and time on the workspace window?

Deploy with fpga after change of chassis.

Hello I'm running a project Veristand 2011 with an NI PXI-8109RT controller, a jury of NI PXI-7852R fpga and analog outputs 5 NI PXI-6733. For development, I used a chassis PXI-1000 b. Now, I have moved the system to a PXI-1045 chassis, and I can't d

Add a USB joystick

Hi, I am a user Veristand 2011 SP1 and I'm working on a project thar runs on PXI. I need to control certain channels with a USB joystick connected to localhost. To do this, I created a device that is customized by using the simple tool of custom devi

NEITHER Veristand DLL models simultaneous execution

Hi all, I have to solve that problem is with my VeriStand workspace: I have a project NIVS with two models of dll (Run/Stop/Pause) execution is monitored in the Versistand workspace by two interface objects user 'Model Control'. I wonder if it is pos

Rate model

I have a problem with the rate of a PXI 8109 RT controller model. I'm running that one model, with simulink and compiled with real-time workshop. Whatever step size I choose real-time workshop, I see the rate of correct model of the window "Add a sim

RTD & Thermocouple sensors Simulation

I am very new in VeriStand, and I would like to ask you what is the best way to implement simulation of VeriStand sensors. I should implement simulation of RTD and Thermocouple VeriStand probes. Problem with temperature sensors are mathematical equat

Use several channels in the order of RT

Following this post, and based on a simple sequence of RT that monitors a single channel, now I want to control multiple channels with setting specific time and level. The logic of this was to pass an array of strings that you want to monitor in the

Error 74 to unflatten string in a device helping custom interface hardware Inline

Hello I am creating a custom device Interface material Inline to communicate on a bus series to Veristand. I want only to communicate via RS232 veristand channel values, I use flatten/unflatten to chain to transfer my data. I choose what it because V

custom device PLC Siemens

Hello I do test with NI Veristand HIL. My hardware is a cRIO 9075 siemens AND 200 s PLC. I found an address ethernet/IP add it to veristand:http://zone.ni.com/devzone/cda/epd/p/id/6337 However, if I understand correctly, it will not work with siemens

Error-307650 during a sequence in real-time with API LV

I created a basic real-time sequence that checks the time it takes a signal reach a certain threshold. On the side of the LV, I use the API to call this sequence. I make sure that all channels and settings are defined as in the examples. However I ge

FPGA-IRQ in the custom VeriStand FPGA VI?

Hello I built an FPGA VI custom to use in VeriStand. This FPGA VI contains the following IRQS: Now I also have a VI in LabVIEW FPGA code that I want to use VeriStand. I changed it to use as a custom device, so I removed all of the FPGA code and repla

editing a procedure in labview

Hello I am changing a variable of procedure which has already created and saved in the system definition file. I would like to call this sys def file, change the procedure and deploy on CRIO through LabVIEW. Is it possible... ?? If so please help me

using the usb key in veristand

Hello Use Embedded data logger custom peripheral in veristand we could record data to the tdms file format located in the "c:\logs" on RT PXI. If I want to access this file, I am the pxi start in windows and then I could only access the file for anal

The upgrade to 2.5.1 Tek Full 2010

I got a demo version of the installed SE - Tek I think it's the version 2.5.1. I downloaded the full version of 2010 and has purchased a license. 2010 installed ok and said it was the upgrade the 2.5.1 existing. When I ran 2010 he came and said it wa

Pouvez PCI-6133 aquire acceleration?

Types of PCI-6133 can include NO acceleration. If I connect did to the PCI-6133, then select the voltage as the type of measure. What dose the acquired signal mean? Is there a relationship between this signal voltage and actual acceleration?

VeriStand alarms

I set an alarm to travel on Estop system. I look at the bit for the lack of a camera and trigger a process when she is off limits. The problem is that the alarm message is not always pop up. the action is triggered another channel seem to work. Is th
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