I have to define several of the FIFO to synchronize a master loop at three other parallel loops?

If I have a single loop to generate a waveform and I mean, three other parallel loops to extract the values from this first loop via a FIFO defined by VI, must I place three separate FIFO components 'Write' (essentially by defining three different FIFOs) on the first lap which correspond to the three elements of FIFO 'Read' in each of the three loops accessing data of the first loop?

The problem with the help of a simple FIFO, is that when a value is read, the value has disappeared.  The other loops will not see this element.  And since it looks you speak too well of FPGA, you would have to worry about arbitration as well.

You need a different FIFO for each loop that you send.

Tags: NI Software

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