Calendar of FPGA away from promises

My enforcement focus on the measurement of time that separates digital TTL. The material used is to cRIO9068 and module 9402 at high speed.  Given that the chain of hardware can run up to 16 MHz and loop simple FPGA can reach 80 MHz clock, I aspected to have for this application precision autour 5 tick (ticks 1 = 12.5ns = 1/80 MHz, 5 ticks is 62.5ns is 1/16 MHz).

Well I can test power squares request to 9402 via a function (high quality) generator. Then the accuracy on the events of time on only mounted (or only fall) TTL is pretty good (10 ticks at 1 kHz) when I use to deal with the two rise and fall events the accuracy became about 60 ticks.

Who is guilty here?

However from what I see these little paper specifications are not answer

rozzilla wrote:

TWL?

I think GerdW meant "Timed While loop", although I have not seen this abbreviation before (and I use LabVIEW FPGA for a long time).

He really need to see your code, and the project file to see how you have configured your top-level clock and derived clocks, in order to provide assistance.

I would discourage you to use the features of comparison (for example, over/under of) to compare Boolean values. Use standard Boolean logic (AND, OR, etc.) instead.

Tags: NI Software

Similar Questions

Maybe you are looking for