I need the code optimization... :))

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  Each table is 2D size 512 by 640.  The time it takes to run this whole chain is approximately 28miliseconds. Seems fast, but I need to cut it to about 10ms.  I tried to make the tables 1 d, but saves only about 2 ms.  I even tried to cut the table 1 d in half and duplicate the code and then combine them at the end (a half-hearted attempt at optimizing multi-core) and who showed zero improvement...

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  If you don't know how you would in C, I don't know why you think that move it to a DLL will make it faster. In C, you will need to either make operations sequentially in a loop for, as you mentioned, or find a library for parallelization of this operation. There is no built-in c function to multiply the tables.

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• Optimization of DMA in the Code in time real (cRIO FPGA-&gt; RT)

  Howdy,

  I am acquiring data from a microphone using the NI9234 module.  I wrote my RT and FPGA code.  I am communication of data between the FPGA and RT layers using a DMA FIFO.  I noticed that the layer of RT has difficulty to empty the FIFO, since the FPGA layer runs at a much faster pace.  I would like some pointers or suggestions on stupid things I do in the layer of RT that are causing it to run more slowly than necessary.

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