Missing VIDEO signals for NOR-5762-(02)

Hello

I installed 15.1.1 FlexRIO, and I use it in LabVIEW FPGA 2013.

I am trying to program the 5762 using the multi-sample CLIP: \Shared\FlexRIO\IO Modules\NI 5762\1.0.0\V5\NI5762MultiSampleClip\Ni5762MultiSampleClip.xml.

By the November 2015 FlexRIO help, I think I'm supposed to use 'data clock/2' for IO nodes:

However, there no such signal in the signal list when I add the CLIP:

So, I followed what are probably mistakes typing in help FlexRIO next to the data signal clock/2 who say, 'IO Module clock 0 must be added to your project in the dialog box properties of the clock of basis of FPGA. The following signals shall be accessible in this area of the clock: I 0 N data, HAVE 0 N-1 data and HAVE 1 N N-1 AI 1 data data. » :

I add IO Module 0 as a base clock clock to the project:

And the dialog box above makes me think that IO Module clock 0 is compiled for 50 MHz, when I expect to be compiled at 250 MHz or 125 MHz.

Exactly how should I clock AI0 AI1 multi-sample IO nodes in the LabVIEW diagram?

Thank you

Steve K

Hi Steve,.

Looking at your path to the XML CLIP code, it seems that you are using the 1.0.0 version of the CLIP.  This does not include the "Data Clock" signal and uses only IO Module clock 0/1.  There were a few additions in the latest CLIP who could have incompatible with Labview 2013, so only one can use the 1.0 version.  The CLIP of 1.0 is good to use; Simply use the clocks of Module e/s.

The clock frequency listed in the IO Module clock 0 properties does not affect the frequency of compilation; the frequency is set by the constraints of the CLIP.  I think that this value is used sometimes when generating constraints for some paths, so I would still recommend the 125 MHz configuration.

Documentation is really confusing, especially in cases like yours helps newer Flexrio with older Labview.

Kyle

Tags: NI Products

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