Schedule my EI Code returning same time value

So I'm running a VI that communicates with a VISA system that we have built to take action. We strive to obtain the temporal measures for how long it takes the device to run his program and communicate in return. I created an Action CheckTime.vi engine for it but for some reason some get the same results with the measures. Once the unit can enjoy 1 time, sometimes the unit will enjoy 5 times based on what we say to do. I would like to return a measure for each measure 1 sample or 5.

This is where the model is checked to determine if, to take another measure, it is when the timer is initialized.

Once reading the data back from the device VISA, we will look at the time as many times as the number of samples taken. For each sample, a new set of data is read and a new time must be pulled out, but data resulting shows several times the same measure.

Here are the results with 5 samples. I think I should get a different measure for each iteration of the loop for.

Maybe my AE is not correct? Or a weird conversion is in fact somewhere?

I suppose you loop For are an iteration if fast time windows has no time for up. Try to use the timer high resolution instead of duration in seconds.

Ben

Tags: NI Software

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    http://targusblog.com/2014/11/25/how-to-turn-a-99-Tablet-into-a-workstation/

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    I have a basic FPGA code that transmits the bits of data on a serial (RS-485) bus, the code is written so that it expects in the first State of a machine to States in a single-cycle timed loop.  After a certain trigger, he begins to read a FIFO containing data and sends the data on a line of Tx.  It does this until all bits are send and then it goes back to the first State to wait for the next trigger.  The relaxation is necessary because windows must fill out first before the FPGA FIFO can start sending.

    I need two instances of this code runs, because I have two buses of com (one is redundant).  So I use the FPGA code as a Subvi and I wrote a main FPGA vi to call two separate instances of the Subvi in parallel.  A regular window vi wrote on the FIFO for bed FIFO for Rx and Tx.  No problems so far.

    The thing is I start two transmissions in 200nS of each other (Yes, nanoseconds).  Windows will write two FIFO in parallel, but the timing is 4uS apart, too long.  I tried implementing a Boolean flag in the Subvi FPGA, but windows can not write directly on the control of Subvi.  FPGA won't allow (the Write function is grayed out).  I tried to use a FIFO for a flag, but the problem is a race condition.  One of the instances is first read FIFO and he destroy.  The other can't read.  I need a common trigger point to be used by the two instances of Subvi.

    My final solution was to use a memory in the Subvi FPGA and digital control in the main FPGA vi.  Windows write in numerical order, it may because the control is in the main FPGA vi.  Inside the main FPGA, I run a timed loop that looks for digital to be zero.  If so, it writes the value into the location of the memory used by the Subvi FPGA.  After awhile, the principal wrote a zero back to memory to prevent the Subvi is restarted, as well as to write a zero for digital to reset.  This repeats, waiting for windows to write in digital again for the next transmission.

    I had to do it this way because sometimes I want to pass on the bus, and sometimes just one or the other.  Numeric values are used to determine which to pass on.  Now, the transmissions are starting to almost exactly at the same time, 1 or 2 nanoseconds apart.  But the trigger process seems very silly to me.  I was wondering if there is a better solution.  I'm pretty new to FPGA.

    tbob wrote:

    Basically, I did the same thing using FPGA memory.  Windows I am writing for a digital control that resides inside the main FPGA vi.  In the main FPGA, I write in the memory.  Inside the Subvi FPGA, I read the brief and decode the value to use either one or the other or both buses.  After fool with it for awhile, because reading Memeory needs to use a shift register (probably because it takes a whole cycle of clock), I had to work.  The two bus trigger at the same time.  I guess it's not really important if I use a FIFO or if I use the memory.  The main problem is that I write Windows at the hand of FPGA, then the hand of FPGA for the Subvi FPGA.  Then the time is right for what is the Subvi is.

    There are some advantages to the use of two FIFO on your approach.  First of all, you don't have the change of register for the memory location.  Secondly, we should not worry that VI is responsible for compensation to the memory location, or do, you run the risk that one of your subVIs run twice, or not at all, if the memory is not erased at the right time.  Perhaps most important, you'll save yourself space on the FPGA because you will not need arbitration - the additional code that is added when two parts of the FPGA try to access the same resource at the same time.  In your case, both instances of the Subvi access the memory block at the same time, so the FPGA compiler adds additional logic to avoid conflict.  If only read you the memory block in one place and just write it in one place (reading and writing can be different loops where subVIs) there is no need for arbitration.  Using two FIFOs, you can keep independent and avoid the conflict resolution code.  See the help for the "arbitration" for more details.

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