Sequence structure flat inside the timed loop and execution order
I have some problems trying to implement a flat sequence structure when you use a loop timed on a target of cRio VI
I tried with or without the while loop around the structure of sequence flat, and I also tried to replace the 'Non-deterministic loop' with a timed loop
The problem is that the program seems to run only once, then get stuck somewhere
I am writing a program that performs the following operations as soon as possible:
1. read the Pos_MC of entry on the FPGA
2 send the value of Pos_MC to the VI target (on cRio CPU)
3. calculate a value of output based on Pos_MC with a PID block ("exit PID')
4. send 'PID output' to the FPGA
5 write "PID output" analog output "MOOG".
In addition, I want the program to return the measured value "Pos_MC" to a host VI for the recording of data
So that the output of PID is calculated and sent to the FPGA as quickly as possible, I placed a flat sequence structure to ensure that it happens before you send the output to the nondeterministic loop for recording data
Also, I want the digital input 'Stop' to be able to stop the loop deterministic (the timed loop)
I read much more entries than that and the help of several PID and exit, but I rewrote the code for a single entry and exit to make it easier to illustrate
Screenshot of the code is shown in 'target code.png' and 'fpga code.png.
The VI themselves are attached in the next post (cannot attach files of more than 3)
Question 1:
Any advice on how to get this race? Thank you!
Question 2:
Is also my correct understanding in that, using this structure, each 0.9ms (fpga loop time) comes the following:
1. the input ("Pos_MOOG") is read on the fpga
2. the production of PID is calculated on the cRio with some delay to computation (for example 0.1ms)
3. the output of PID is then written for analog output "MOOG" in all about 0, 1 - 0.2ms
4. the FPGA program then waits until 0.9ms spent and repeat the process
As opposed to the next pass whenever performing a loop is started on the FPGA:
1. the FPGA reads the input and written on the output (the output of the execution of the previous loop PID)
2. then the entry is sent the cRio, PID output is calculated and sent to the FPGA
3. the new release of PID is maintained until the next time through the loop
Thank you!
PHG wrote:
Thanks for the input guys, any advice as to how I could get the feature in scenario 1?
I still say that the best route is just putting all the logic of the control in the FPGA.
Other alternatives include 1) the use of DMA FIFO sedn data back or 2) use interruptions so that the FPGA code can not read the output level until the RT.
DMA FIFOs are usually very limited, and I would not use them in this situation since I belive said it this code to do for the many outputs.
Tags: NI Software
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