Strange problem with my FPGA Code

Hello

I am running the following program, but I am facing a strange problem:
-I can read all analog and digital input and write on the outputs analog (I measure the tension that I write on the map of the AO)

- But the valves I have connected to the analog output, flashes a red light (which, according to the data, sheet means the electrical signal I send to them via the module AO is incorrect)

-However, if I delete the ms and RMS block and do not make any average samples, but let all even (still two loops and two of the nodes separated from FPGA to e/s), the valves are operational and flash not a red light.

I have a cRIO with four modules:
-1. The (Mod1) AO cards
-2. Map of HAVE it (2)
-3. DI/O card (Mod 3)
-4. Map to HAVE secondary (Mod4)

I currently have two loops on the fpga all-in:
-' Hand Loop (ML)': reads and writes I/O cards 1-3, with an expectation to 300us
-'Top pressure sensors Loop (PACKAGE)' reads two HAVE the fourth module (Mod4), with no waiting

These two loops are indicated in "fpga - part 1.png" and "fpga - part 2.png".

The settings for the ms and RMS measures VI, as well as the façade are indicated in "fpga - part 3.png".

The second loop uses 12002 ticks to run, the first loop use 160 ticks to run

Previously, I had a similar problem which was fixed by setting the initial values indicated on the front cover for the analog output to the valves.

Currently, I have not any target VI race and I'm only using fpga VI

Any suggestions? Thank you!


Tags: NI Software

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