Violation of FPGA Timing-> how to find?

Hello

I encountered a problem of violation of timing during my FPGA code compilation. Even if I change the options of compilation for "balanced" or anything else, the problem is still there.

My question now is, how do I find the function block in my code where the problem occurs? I use the SCTL several in my code.

Thanks in advance

Use the controls for the FPGA-host communications as long as you have enough of FPGA resources. It is recommended to use the communication between the host and FPGA DMA FIFO.

Only controls on the higher-level FPGA vi are accessible on the side of the host.

Global variables are used to communicate with an FPGA scope exclusively.

You use a device of sbRIO so I think the FPGA to communicate with the aim of RT (host)...

Tags: NI Software

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