5154 digitizer for fpga data

I am trying to stream as quickly as possible from the to a FlexRIO 7966 5154 digitizer. From the example "NISCOPE fetch Forever" in LV2012, I can implement the acquisition on 5154 @ 40MS/s, 50 k of data I8 piece and the graphical indicator seems to keep well indefinitely.

I tried then write data to an FPGA - FIFO target host, and it chokes. With FIFO write the method inside the loop of 5154 fetch the 5154 ends in error because of the "overwhelming memory" (it fills its on-board memory until the HOST is reading). With FIFO writing in a parallel consumer (queue conduit) loop, the queue overflows just because he can't write that as fast as the 5154 FIFO provides samples in the queue. What Miss me? The 5154 uses a PCI DMA bus (I think), so I think that if he could hold, the host to the FPGA PCIe bus must be capable.

There is another factor, that I have not taken into account? Sorry I can't provide the VI since the installation of the LV is on a PC not connected to the network. Any advice or suggestions would be appreciated.

Thank you

Mark Taylor

For future reference, I ended up resolving this by moving the implementation on the actual FPGA. I had run in mode "on the development computer with i/o simulated" and no matter what I did with the start-up or sizing FIFO sequence, it just doesn't work.

After compiling and running on the FPGA, all right. Maybe it's the basic knowledge, in fact I remember somewhere in my travels reading that don't accurately represent timing problems when running to the old fashion, but LV FPGA has kind of us painted into a corner with the compromise of simulation/compilation. They do not include Modelsim, which is the only tool that enables co-simulation do functional and verification of the timing set (we Questa, unfortunately) and independent VHDL simulation captures the interaction host with precision (and software processing/timing is impossible to quantify!). In my situation, the only way to operate at speed is in the FPGA, but then I can't see all of the things that I need to see to debug... ARGH!

Additional links and resources always will welcome (on debugging of FPGA LV and design in general). I found a couple of things below, which was somewhat useful:

"NEITHER powerful LabVIEW FPGA Developer's Guide"

http://www.NI.com/Tutorial/14600/en/

I found a link to an "FPGA Debug Reference Library": http://www.ni.com/example/31067/en/, but my installation does not seem to have this available.

And it looks like 2013 may add functionality to help alleviate some of this via the node of the execution of office referred here to the 'Test and debug LabVIEW FPGA Code'

http://www.NI.com/Tutorial/51862/en/

Tags: NI Software

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