Coregen MACC

Similar Questions

• Coregen memory when you use defined VI block memory

  I currently have a problem when you try to compile a VI for my card Flex RIO (SMU-7965R).  I have a sub - vi which contains a small instance memory set by VI (U16 X 256 elements) and a block of DSP48.  This VI is instantiated 128 times in the top level VI.  When I set up the memory set by VI to target the block of RAM in the FPGA, the compilation process is suspended during the generation of the nuclei (memory after ~ 45 min).  LabVIEW treats each instance of as single block memory when executing coregen?  I do not experience this problem when I set up the memory set by VI using LUTs.  Any thoughts would be appreciated.

  Thank you

  Brian

  Hi Brian,.

  I believe that this compilation failure could be less related to the implementation of memory coregen, rather the memory of the way that is implemented in the lut and block memory on an FPGA. Lut are built through flip-flops and are perfect for storing information 100-300 bytes, while the memory block is segmented in a fixed size of 2 k RAM embedded. There are only a number of structures of block of RAM in a given FPGA and it seems that in your case that you use more of your resources block of allocated RAM. For example, in the 7831R if we tried to implement a FIFO in the maximum possible storage size block memory would be 81 920 bytes due to the limitation of resources.

  The implementation of flip flop of the LUTs will allow the compiler greater flexibility in the use of resources in compiling because the size of the LUT is not fixed in the way that is a block structure of RAM. This is probably the reason why this LUT implementation is compiling successfully while the RAM block is not in this case.

  Kind regards

  Blayne K

• Xilinx Coregen does not appear in the palette

  I would like to you can generate FIFO for my LabVIEW FPGA Xilinx Coregen project. The help file says to look on the palette of programming within an FPGA VI, but I did not. I have the node IP integration and all the functions the FPGA but not Coregen. The application itself is installed on my computer. Is there an installation option that I missed? How can I get this appears?

  Rgds,

  Nick

  The .ngc file IS the netlist.  It must be built next to the file .xco in the process of Coregen.  It must have the same name (for mine, I named the generated_fifo component) If you want to see generated_fifo.xco, generated_fifo.ngc, and there should also be a generated_fifo.vhd.  The .xco file is essentially a list of coefficients and build the basic settings.  The .ngc file is a synthesized version of the kernel that used the file .xco for the generation.  The .vhd file is a simulation of the core model.  Usually, it won't not synthesized, but can be used for the simulation.

  Thus, the only file you need to add in the configuration of the node would be the .ngc file (which is the netlist).  You will then need to configure the behavior of simulation to use the corresponding simulation .vhd file or use a post-synthese model.

• Download ibook

  Hi my name is miguel. I write this email if your help me I buy an ibook Apple store. I have the problem cannot download for not having Apple and iPhone and MACC. I have the computer Windows vista 7, I would like to know how I can download and play with Windows vista 7. There is an application to download and read the book eliminated the DMR and download it to my computer. I have download and can read the book in my computer.thanks miguel.

  iBooks is not compatible with Windows

  Google Books

  https://books.Google.com/bkshp?hl=en & Tab = WP & AuthUser = 0 & ei = aWnZV-6GFsjR-QGH5KrwCQ & ved = 0EKkuCBAoEA

  
  

  eBooks-Windows Vista 7 - Google search

  https://www.Google.com/search?NUM=20 & newwindow = 1 & hl = in & site = webhp & source = HP & q = EB are + windows + vista + 7 & oq = ebooks + windows + vista + 7 & gs_l = hp.3... 1544.1544.0.2571.2.2 0.0.0.0.146.259.0j2.2.0... 0... 1 c. 1. 64.HP... 0.0.0.0.ZGyIobUjmeQ

  iBooks - read a book purchased from iTunes on Windows epub - ask different

  http://Apple.StackExchange.com/questions/104544/read-EPUB-book-purchased-from-it each-we-windows

• Can I replace the graphics card on Satellite Pro A100

  Hi all

  Just a quick question about the graphics card in my Satellite pro a100 computer laptop. I heard different stories about this.

  The ATI RAdeon Mobility x 1400 card can be replaced on this laptop. If so how easy it is to do and how I could tell which cards would be compatible?

  Thank you

  MAcca.

  You cannot remove, replace or update the graphics card.
  The graphics chip is attached to the motherboard and it of not possible to remove it.
  In addition, the motherboard is compatible only with the current graphics chip.

  Good bye

• Satellite Pro A100: How to get updates for driver for ATI Radeon Mobility X 1400

  Hello

  I am aware that the driver for my on-board graphics card is outdated.
  When I download a updated from ATI driver and try to install, it tells me that I can't install the update the system there and contact Toshiba for the updates.

  Please can someone tell how can I get a driver updates for this card on my Satellite Pro A100 series?

  Concerning

  Macca.

  Hello

  You can not install drivers ATI ATI site because these drivers are not designed and certified for Toshiba laptops.
  These drivers can affect the functionality of notebooks and in worst cases could overheat your GPU

  * So if you want to use these drivers, you can do it but only at your own risk! *

  You can install this driver in Device Manager;
  You must use the Advanced installation procedure and you will have to indicate where the graphic driver files were stored on the HARD drive

  Good bye

• Update driver for ATI Mobility x 1400-Satellite Pro A100

  Hello

  I have the above card in my Toshiba Satellite Pro A100. Does anyone know if Toshiba published or publish updates driver for this card and if so, how to get them?

  Thnx

  Macca

  Hello

  To be honest, there is no much of philosophy. If Toshiba offers updates, these drivers will be available on the Toshiba support page. If it isn't...

• Diablo 3 graphic card

  Hi everyone wondering if anyone could offer some advice. My son downloaded the new diablo 3Ave game and the graphics card I have in my HP pavillion slimline s5206uk is not compatible. Does anyone know the compatible card that I can go to work with my machine. I read that the slimline machine will take only some cards due to the design slimline etc. The machine meets all other requirements of the system except the graphics card. My apologies if I posted this in the wrong place. Any help would be appreciated

  Thanks in advance

  Macca

  Macca, welcome to the forum.

  Slimlines are perfect for many reasons.  However, game is not one of them.  Simply, they are not intended to be upgraded.  The case does not have enough air.  In addition, the power supply unit (PSU) is only to 220W.  The video card that will work with it be much, if any, better than the integrated video.  I know this isn't what you wanted to hear, but I don't want you to spend money unnecessarily.  Modern games require a lot of power.

  If your problem is solved, please click "accept as a Solution.

• satalite 4000cds: I need a graphic driver XP!

  I just installed windows xp on the computer and I am unable to find the driver for the graphics card, could someone help

  Thanks macca

  Hi André,.

  You should be able to find all the necessary drivers on the Toshiba web site.

  For the USA http://www.toshiba.com/
  for Europe http://uk.computers.toshiba-europe.com/

  HTH

• Very unstable WIFI connection on Satellite A200 PSAE4E

  Just had my Equium A100 replaced with a satellite pro A200 and for some reason that I am fighting to get it connected to my wireless network. I had the old laptop connected properly and used channel 11 on my WAP.

  Now, after trying to connect my new laptop I find the connection very unstable. I tried different channel numbers, and these worked mainly the lower numbers, but are proved to be slow and unreliable. I have other laptops that are very well using my WAP to channel 11.

  Anyone who has experienced this trouble and what is the solution.

  WAP Netgear wg602. No firmware update available

  See #.

  Macca

  Hello

  Just a question: do you use pre-installed Vista or maybe WXP on your new laptop computer?

• Low pass FIR Filter on FPGA

  Hey guys,.

  I the DFD Toolbox and already built a few low pass FIR filter. I have a sampling rate of 50 kHz and I decimate it with a CIC filter with rate variable decimation. After the CIC filter, I need a high-grab for the low-pass filter FIR because I do want my DC signal. As I can change my rate of decimation, my FIR filter sampling rate changes also.

  The problem is that the coefficients of the filter cannot be changed during execution as the Butterworth IIR-filter function, including labview has implemented in the mathematics of the fpga function palette section.

  Are there examples how to build FIR filters where I can change the coefficients on the run?

  Think you can build a low pass FIR with the DFD toolkit and simply change the table with the coef. for a control? I could change them on the track...

  Greetz

  Slev1n

  Hi Slev1n,

  just found it in the community, maybe this might help you already:

  Polyphase Interpolation FIR Filter on FPGA with Diabaté and Coregen

  https://decibel.NI.com/content/docs/doc-16650

  Greetings

  Michael

• FPGA ni922 24 bit?

  I am trying to acquire data from a ni9222 located in the chassis-9014 9114, cRIO.

  But for some reason, the output data type is used as a 24-bit fixed point number?

  However the 9222 is module of the ADC 4 channels 16-bit 500ks/S.

  I want to run the data via a fifo (target scoped) to power a 2 channel FFT module (coregen), which accepts fixed point 16-bit numbers.

  I seem to be anyway to change or correct the accuracy.

  I increased the fifo to 24 bits to try to work around the problem, but then I can't seem to massage the 16-bit required format (that it should have been originally)

  All this in the area of the chassis/FPGA

  In another section of my main FPGA vi, I 16 bits of the data of NI9215 quite happily was sent down a DMA FIFO for the time real cRIO and connected to a USB key without any strange problems.

  PS are the example any screws available for the use of the FIFO coregen and the 7.1 FFT coregen?

  I use the labview 11

  In my view, that the data is being multiplied by a scale factor to convert the entry to volts instead of charges.  I think it's so when you mix different modules with different resolutions of data acquisition, the outputs are in volts and can be compared, etc..  I know that I changed the properties of some modules for the former counties old-fashioned, but I don't remember exactly how I did it.

  Bruce

• [FPGA] xilinx ise?

  Hello

  I am trying to configure a component LabVIEW and xilinx coregen won't let me because «is not installed with labview fpga xilinx ise» I can't find a proper download of NOR. Is this a question expected? There is of course the xilinx website, but do I need a specific version and how can I say? The target FPGA's Virtex-6 LX195T if that's a factor. LabVIEW 2013.

  http://sine.NI.com/NIPs/CDs/view/p/lang/en/NID/210629

  Hey, ToeCutter,.

  You have the 2013 LabVIEW FPGA Module Xilinx tools installed locally? Who has Xilinx coregen, which is what you will need to configure their intellectual property. If you are some intellectual from the LabVIEW FPGA palette, it should "work".

• Problem compiling LV FPGA (urgent)

  Hello

  I'm trying to make a code FPGA LV in my crio 9074, but it takes a lot of time unsusually (40 minutes or more).

  I'm trying to implement this example to generate a waveform: http://www.ni.com/example/28209/en/

  Up to now, it's show "generation of carrots" message and in the newspaper, I'm repeatedly getting this message:

  aved CGP file for project 'coregen.
  Fix generics to 'ReallyLongUniqueName_ReallyLongUniqueName '...
  Generic external application to 'ReallyLongUniqueName_ReallyLongUniqueName '...
  Delivery of files related to "ReallyLongUniqueName_ReallyLongUniqueName"...
  Setting netlist generation implemented to
  'ReallyLongUniqueName_ReallyLongUniqueName '...
  Synthesis running for "ReallyLongUniqueName_ReallyLongUniqueName."
  13.4 - Xilinx CORE Generator O.87xd (nt) of output
  Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
  Save all the run-time messages
  C:\NIFPGA\jobs\W543T9Q_a5T1mXb\coregen.log
  In the CGP project «coregen» file
  Fix generics to 'ReallyLongUniqueName_ReallyLongUniqueName '...
  Generic external application to 'ReallyLongUniqueName_ReallyLongUniqueName '...
  Delivery of files related to "ReallyLongUniqueName_ReallyLongUniqueName"...
  Setting netlist generation implemented to
  'ReallyLongUniqueName_ReallyLongUniqueName '...
  Synthesis running for "ReallyLongUniqueName_ReallyLongUniqueName."

  It seems that it is in some kind of loop without end Peae guide me how to solve the problem.

  Thank you...

  These are 'normal' of the process of compilation output messages (although they are a little curious). It is normal to have a certain number of these modules in the FPGA design, if you use analysis library functions; each of them can take several minutes to synthesize. The compilation has finished?

  Fortunately, if you're doing only minor subsequent changes compile compile times are expected to decline because the compiled results of each of these components is cached.

• FPGA compilation I get error & quot; ERROR: ConstraintSystem:58 & quot;

  I use the Xilinx LogiCore IP generator for generating DSP IP for my FPGA.

  The problem is that the names of the generated components are for a long time.

  On the Web site or http://digital.ni.com/public.nsf/allkb/F810E4289A420FE68625796600764C66

  He described a problem very similar to what I have ID issue 309260 "compilation error (ERROR: ConstraintSystem:58) when compiling a LabVIEW FPGA VI which contains a generated from a DSP graph VI.»

  I followed the suggestions and changed my IP to names such as 'A' and 'B '. As a first step, that it did not work, only to spend the entire project to another shorter path of directory did this job.

  Now, when I regenerate the IP address of 'Tools' > 'FPGA Modules' > "Regenerate the node IP" this will rename my IP with an additional random name at the end. So, if I look in my case not only that I have "A.vhd" but now, I'm also having 'A_F27AB4F7464E508DCCB219B2C4271B18.vhd '.

  It's very repetitive, and you should be able to replicate that.

  It's havoc with our software and with our software process control tool. Our database of software can accommodate only names of files of a certain length, and this violates. Also, I now have files with the exact same content but with different names.

  Do you have a fix for this problem as stated on your website?

  Kind regards

  I ended up using LogiCore externally. If you do a search in your LabVIEW FPGA tools folder, you should find "\Xilinx12_4\ISE\bin\nt\coregen.exe" (in the case of the specific version of Xilinx tools you have), it's the Xilinx Logicore exe without the National Instruments candy wrapper.

  I created all of my external LogicCore to LabVIEW (it actually makes life easer, the LogicCore tool has a better Manager to track all your IP LogicCore in any case) and then used the IP LabVIEW nodes to access the intellectual property.

  This has prevented the long names, and now I can better handle the INVESTIGATION period because I can put the code in a folder I want without breaking of LabVIEW.

  -good luck