FPGA RAM block access protection?

LabVIEW FPGA puts any type of protection around the block RAM (BRAM) access?  In other words, if I have the same accessible BRAM from several loops in the FPGA, some reading, writing, some in the same loop possibly writing to different addresses at the same time (at least, in the stream, they appear simultaneously), LabVIEW use something like a semaphore to limit access to one at a time?  I don't see the advantage of using FIFO on BRAM either, as these loops run at very different speeds (some update of memory, others pull memory to write to i/o).

Otherwise, what is the best method to implement this protection on the FPGA?

I saw an example of a semaphore by using one FIFO Boolean defined by VI in a reentrant sub - VI, likely implemented in flip flops (implementation being an addition of LV 2012 options?).

I use 94% of my slices in the sbRIO-9636 right now, so I wouldn't have a bunch of semaphores waste of resources if they are not needed.

Also: I've set many distinct BRAMs.  Does make sense to have separate semaphore, or accessed using the same address lines, all of the BRAM do a single semaphore, the only way to protect them?

Thank you

Erik

Hi Erik,

BRAM is protected.  I believe you are referring to this white paper Web site: http://zone.ni.com/devzone/cda/epd/p/id/6014

He protected in accordance with this statement: "more shared resources in LabVIEW FPGA, this is handled automatically and the code is added during the code generation process."

Thank you!

Tags: NI Software

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