How the resets are generated in LabVIEW for FlexRIO

All,

My background is VHDL and Verilog for FPGA and ASIC implementations.  I guess LabVIEW has a point, an only synchronous reset to all of its logic.  I create a design that is going to be sections of VHDL IP, through IP integration node is instantiated. When writing to the top of my spec, I need to describe how a reset is spread to all the flops in the design that will be peer-reviewed of accuracy of the results. I need to understand exactly how LabVIEW handles resets to other areas of the clock.

A simple case is the following: I have a 50 MHz external source synchronous data interface and will be a limited treatment of data in this area of 50 MHz using an IP integration node. This IP is designed to have the flops to reset synchronous on the 50 MHz clock.

Separately, I have my most of my treatment and storage to the host (via DMA FIFO) in a field of 100 MHz clock, derived from the clock of 40 MHz I base I must transfer data from 50 MHz to 100 MHz using a FIFO.  This treatment at 100 MHz contains a floating-point operations that are reset to zero synchronously to the field of 100 MHz.

In this scenario, you see I have two areas of clock with synchronous resets.  I need to understand how LabVIEW FPGA create reset signals which are entries to my integration IP nodes, in order to understand if I need to incorporate any reset synchronization within my VHDL circuits.

Thanks for any help and if you need further details or context, please let me know and I find out additional details.

-Jim

Hey Jim,.

So, option 2 then... in this case, you are looking at a signal of asynchronous reset and must realize in your VHDL similar to the following to ensure that your resets are say synchronously.

Tags: NI Software

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