How to stop the series 'VISA read' the sends packets instead of bytes available.

Dear Labvillians,

Highlights:

How can I stop series "VISA read" send me packages rather bytes?

Background:

I have a system which publishes series of 14 bytes on a semi-regular interval packets.

At busy times, the producer of these these queues of data packets, effectively producing Super-paquets multiple of 14 times larger than 8 packages (112 bytes) bytes.

My protocol handler is designed to process bytes, packets, or packets Super.

Now, my request has multiple devices and the order of message processing is essential to the proper functioning.

My observation is that read VISA waits until the end of a package / super package before moving the data to the application code. (See chart below)

My expectation is that VISA read should give me bytes available, get too smart for itself and not wait for a package.

.

I noticed this on PXI, PC shipped, PSC and, more recently, cRIO

I've experimented with Scan interface the cRIO rate, which helps to reduce the backlog of packages but don't decide to package under read byte.

I understand that a solution is FPGA code write to handle and pass the bytes by R/T-FIFO, and there are some great examples on this site.

Unfortunately, it does not help with FPGA devices not.

I have also dabbled in the event based sequential reads, but he is evil on vxWorks devices.

Any help is appreciated

It is helpful to sometimes talk to yourself.

I hope that is useful for someone sprinkle in the future

Tags: NI Software

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